[PATCH] Arm Initialize SP for Cortex-R in semihosting case

Alexander Fedotov <[email protected]>
Newsgroups gmane.comp.lib.newlib
Message-ID <CAN8C2CoLVbNWe_HNQjP=h2tFvGrGT6vqbzNVprPf-CLdgp7Q9A@mail.gmail.com>
Since Cortex-R cores doesn't have NVIC and therefore no hardware stack
pointer initialization we have to force SP initialized by default
value and then override if optional value is passed over HeapInfo

Alex
0001-Initialize-Stack-Pointer-by-default-value-in-semihos.patch (application/octet-stream, 1.1 KB)
From d35b3554633cb338e9209d71f56fc62f68462c33 Mon Sep 17 00:00:00 2001
From: Alexander Fedotov <[email protected]>
Date: Wed, 23 Jan 2019 13:33:14 +0300
Subject: [PATCH] Initialize Stack Pointer by default value in semihosting case
 and then override if optional value is passed

---
 libgloss/arm/crt0.S | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/libgloss/arm/crt0.S b/libgloss/arm/crt0.S
index 48f3d6b1d..c8fea5251 100644
--- a/libgloss/arm/crt0.S
+++ b/libgloss/arm/crt0.S
@@ -148,11 +148,15 @@
 	      to skip setting sp/sl to 0 here.
 	    - Considering M-profile processors, We might want to initialize
 	      sp by the first entry of vector table and return 0 to SYS_HEAPINFO
-	      semihosting call, which will be skipped here. */
+	      semihosting call, which will be skipped here.
+	    - Considering R-profile processors there is no automatic SP init by hardware
+	      so we need to initialize it by default value. */
+	ldr	r3, .Lstack
 	cmp	r1, #0
 	beq	.LC26
-	mov	sp, r1
+	mov	r3, r1
 .LC26:
+	mov	sp, r3
 	cmp	r2, #0
 	beq	.LC27
 	/*  allow slop for stack overflow handling and small frames */
-- 
2.20.1.windows.1
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