Re: [PATCH 02/12] RISC-V: memmove() size optimized version: Use compressed registers only

LGTM

On Wed, Apr 9, 2025 at 2:55 PM m fally <[email protected]> wrote:
>
> Change register t1 to register a4, so that the affected instructions
> can be compressed. Since now we have less registers available, the
> following changes need to be made:
> In the previous version of this function, a4 was used to hold the offset
> that needs to be added to source and destination addresses before copying
> any data in the case of source address > destination address.
> Since a4 now holds the destination address, this offset is not calculated
> anymore. Instead, the value in a2 (the number of bytes to be copied) is added
> to the source and destination addresses. Therefore, in the case of
> source address > destination adress, a value of 1 needs to be subtracted
> from both addresses before starting the copying process.
>
> Reviewed-by: Christian Herber <[email protected]>
> Signed-off-by: m fally <[email protected]>
> ---
>  newlib/libc/machine/riscv/memmove.S | 16 ++++++++--------
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/newlib/libc/machine/riscv/memmove.S b/newlib/libc/machine/riscv/memmove.S
> index 0f7216a68..123ab3834 100644
> --- a/newlib/libc/machine/riscv/memmove.S
> +++ b/newlib/libc/machine/riscv/memmove.S
> @@ -16,22 +16,22 @@
>  memmove:
>    beqz a2, 2f
>
> -  mv t1, a0
> +  mv a4, a0
>    li a3, 1
>    bgtu  a1, a0, 1f
>
>    li a3, -1
> -  addi  a4, a2 , -1
> -  add t1, t1, a4
> -  add a1, a1, a4
> +  add   a4, a4, a2
> +  add   a1, a1, a2
>
> +3:
> +  add   a4, a4, a3
> +  add   a1, a1, a3
>  1:
>    lb a5, 0(a1)
> -  sb a5, 0(t1)
> +  sb a5, 0(a4)
>    add   a2, a2, -1
> -  add   t1, t1, a3
> -  add   a1, a1, a3
> -  bnez a2, 1b
> +  bnez a2, 3b
>
>  2:
>    ret
> --
> 2.49.0
>