[PATCH v4 05/11] libgloss: mips: Fixes and improvements for CM3 bootcode

From: Matthew Fortune <[email protected]>

Signed-off-by: Jovan Dmitrović <[email protected]>
---
 libgloss/mips/boot/init_cm3l2.S        | 22 ++++++-------------
 libgloss/mips/boot/init_cm3l2_predef.S | 30 +++++++++++---------------
 libgloss/mips/boot/reset.S             |  4 ++++
 libgloss/mips/boot/reset_predef.S      |  4 ++++
 4 files changed, 27 insertions(+), 33 deletions(-)

diff --git a/libgloss/mips/boot/init_cm3l2.S b/libgloss/mips/boot/init_cm3l2.S
index 2efbbe61e..4ac9b0be2 100644
--- a/libgloss/mips/boot/init_cm3l2.S
+++ b/libgloss/mips/boot/init_cm3l2.S
@@ -66,14 +66,15 @@ disable_cache:
 	/* Read CMGCRBase to find CMGCR_BASE_ADDR */
 	PTR_MFC0 t1,C0_CMGCRBASE
 	sll	t1, t1, CMGCR_BASE_ADDR_LSHIFT
-	li	CM3_BASE, 0xb0000000		/* Make it virtual */
+	li	CM3_BASE, 0xa0000000		/* Make it virtual */
 	or	CM3_BASE, CM3_BASE, t1
 
 	/* Disable L2 cache by setting it to bypass mode */
-	PTR_L	t0, GCR_L2_CONFIG(CM3_BASE)
+	PTR_L	a0, GCR_L2_CONFIG(CM3_BASE)
 	li	a2, 1
-	ins	t0, a2, GCR_L2_BYPASS_SHIFT, GCR_L2_BYPASS_BITS
-	PTR_S	t0, GCR_L2_CONFIG(CM3_BASE)
+	ins	a0, a2, GCR_L2_BYPASS_SHIFT, GCR_L2_BYPASS_BITS
+	PTR_S	a0, GCR_L2_CONFIG(CM3_BASE)
+	sync
 ret:
 	jr	ra
 END(__init_l23cache)
@@ -82,11 +83,11 @@ LEAF(__init_l23cache_cached)
 	/* Read CMGCRBase to find CMGCR_BASE_ADDR */
 	PTR_MFC0 t3,C0_CMGCRBASE
 	sll	t3, t3, CMGCR_BASE_ADDR_LSHIFT
-	li	CM3_BASE, 0xb0000000		/* Make it virtual */
+	li	CM3_BASE, 0xa0000000		/* Make it virtual */
 	or	CM3_BASE, CM3_BASE, t3
 
 	/* Read GCR_L2_CONFIG */
-	PTR_L	t2, GCR_L2_CONFIG(CM3_BASE)
+	move	t2, a0
 	ext	t3, t2, GCR_L2_SL_SHIFT, GCR_L2_SL_BITS
 	beqz	t3, done_cm3l2cache		# No L2 cache
 
@@ -118,15 +119,6 @@ LEAF(__init_l23cache_cached)
 	sw	zero, (GCR_TAG_ECC+4)(CM3_BASE)
 	sync
 
-	/* Reg exists, L2 cache does TAG/DATA ECC. */
-	li	t0, 0x8000FFFF
-	and	t2, t2, t0
-	/* LRU is updated on store tag operation */
-	li	t0, (1<<GCR_L2_LRU_WE_SHIFT)
-	or	t2, t2, t0
-	sw	t2, GCR_L2_CONFIG(CM3_BASE)
-	sync
-
 	li	a2, 0x80000000
 
 next_cm3l2cache_tag:
diff --git a/libgloss/mips/boot/init_cm3l2_predef.S b/libgloss/mips/boot/init_cm3l2_predef.S
index c8e1d5e3e..83be64bf2 100644
--- a/libgloss/mips/boot/init_cm3l2_predef.S
+++ b/libgloss/mips/boot/init_cm3l2_predef.S
@@ -41,7 +41,7 @@ MIPS_NOMIPS16
 # ifndef C0_CMGCRBASE_VALUE
 #  error "Static CM3 cache initialization decisions require C0_CMGCRBASE_VALUE"
 # else
-#  define C0_CMGCRBASE_ADDR ((C0_CMGCRBASE_VALUE << 4) | (0xb << 28))
+#  define C0_CMGCRBASE_ADDR ((C0_CMGCRBASE_VALUE << 4) | (0xa << 28))
 #  ifndef GCR_L2_CONFIG_VALUE
 #   error "Static CM3 cache initialization decisions require GCR_L2_CONFIG_VALUE"
 #  endif
@@ -54,9 +54,9 @@ MIPS_NOMIPS16
 #undef SSET_SIZE
 #undef SASSOC
 
-#define SLINE_ENC    ((GCR_L2_CONFIG_VALUE & GCR_L2_SL_MASK) >> GCRL2_CFG_SL_SHIFT)
-#define SSET_ENC    ((GCR_L2_CONFIG_VALUE & GCR_L2_SS_MASK) >> GCRL2_CFG_SS_SHIFT)
-#define SASSOC_ENC    ((GCR_L2_CONFIG_VALUE & GCR_L2_SA_MASK) >> GCRL2_CFG_SA_SHIFT)
+#define SLINE_ENC    ((GCR_L2_CONFIG_VALUE & GCR_L2_SL_MASK) >> GCR_L2_CFG_SL_SHIFT)
+#define SSET_ENC    ((GCR_L2_CONFIG_VALUE & GCR_L2_SS_MASK) >> GCR_L2_CFG_SS_SHIFT)
+#define SASSOC_ENC    ((GCR_L2_CONFIG_VALUE & GCR_L2_SA_MASK) >> GCR_L2_CFG_SA_SHIFT)
 #define SLINE_SIZE   (2 << SLINE_ENC)
 #define SSET_SIZE    (64 << SSET_ENC)
 #define SASSOC	      (SASSOC_ENC + 1)
@@ -65,10 +65,11 @@ MIPS_NOMIPS16
 LEAF(__init_l23cache)
 	li	CM3_BASE, C0_CMGCRBASE_ADDR
 	/* Disable L2 cache */
-	PTR_L	t0, GCR_L2_CONFIG(CM3_BASE)
-	li	a2, 1
-	ins	t0, a2, GCR_L2_BYPASS_SHIFT, GCR_L2_BYPASS_BITS
+	/* Reg exists, L2 cache does TAG/DATA ECC. */
+	/* LRU is updated on store tag operation */
+	li	t0, GCR_L2_CONFIG_VALUE | GCR_L2_BYPASS_MASK
 	PTR_S	t0, GCR_L2_CONFIG(CM3_BASE)
+	sync
 
 	jr	ra
 END(__init_l23cache)
@@ -96,16 +97,10 @@ LEAF(__init_l23cache_cached)
 	sw	zero, (GCR_TAG_DATA+4)(CM3_BASE)
 	sw	zero, GCR_TAG_ECC(CM3_BASE)
 	sw	zero, (GCR_TAG_ECC+4)(CM3_BASE)
-
-	/* Reg exists, L2 cache does TAG/DATA ECC. */
-	li	t1, (GCR_L2_CONFIG_VALUE & 0x8000FFFF)
-	/* LRU is updated on store tag operation */
-	li	t0, (1<<GCR_L2_LRU_WE_SHIFT)
-	or	t1, t1, t0
-	sw	t1, GCR_L2_CONFIG(CM3_BASE)
 	sync
 
-	lui	a2, 0x8000
+	li	a2, 0x80000000
+
 next_cm3l2cache_tag:
 	cache	Index_Store_Tag_S, 0(a2)
 	addiu	a0, a0, -1
@@ -114,10 +109,9 @@ next_cm3l2cache_tag:
 #endif /* SLINE_ENC != 0 */
 
 done_cm3l2cache:
-	move	a2, zero
-	PTR_L	t0, GCR_L2_CONFIG(CM3_BASE)
-	ins	t0, a2, GCR_L2_BYPASS_SHIFT, GCR_L2_BYPASS_BITS
+	li	t0, GCR_L2_CONFIG_VALUE
 	PTR_S	t0, GCR_L2_CONFIG(CM3_BASE)
+	sync
 
 	jr	ra
 END(__init_l23cache_cached)
diff --git a/libgloss/mips/boot/reset.S b/libgloss/mips/boot/reset.S
index 3abae9528..37c674d82 100644
--- a/libgloss/mips/boot/reset.S
+++ b/libgloss/mips/boot/reset.S
@@ -73,6 +73,8 @@ $Lnot_nmi:
 	 * This could be done from cached code if there is a cca override or similar
 	 */
 	jal	__init_l23cache
+	/* Save the L2 config register */
+	move	s0, a0
 
 	/* Initialize the L1 instruction cache */
 	jal	__init_icache
@@ -93,6 +95,8 @@ $Lnot_nmi:
 	lui	a2, %hi(__init_l23cache_cached)
 	addiu	a2, a2, %lo(__init_l23cache_cached)
 	beqz	a2, 1f
+	/* Pass in the L2 config register */
+	move	a0, s0
 	jalr	a2
 1:
 	/* Initialize the L1 data cache */
diff --git a/libgloss/mips/boot/reset_predef.S b/libgloss/mips/boot/reset_predef.S
index b50d9e4f3..d987ef7f0 100644
--- a/libgloss/mips/boot/reset_predef.S
+++ b/libgloss/mips/boot/reset_predef.S
@@ -81,6 +81,8 @@ $Lnot_nmi:
 	 * This could be done from cached code if there is a cca override or similar
 	 */
 	jal	 __init_l23cache
+	/* Save the L2 config register */
+	move	 s0, a0
 #endif
 
 #if defined(ILINE_ENC) && ILINE_ENC != 0
@@ -105,6 +107,8 @@ $Lnot_nmi:
 #if !defined(HCI)
 
 #if (defined(SLINE_ENC) && SLINE_ENC != 0) || (defined(MEM_MAPPED_L2C) && MEM_MAPPED_L2C != 0)
+	/* Pass in the L2 config register */
+	move	a0, s0
 	/* Support initialising L2 with L1 cache enabled */
 	jal	__init_l23cache_cached
 #endif
-- 
2.34.1