Re: [RFC PATCH] riscv: add vectorized sin

       Dear Pincheng,

> The worst-case error is <= 1 ULP.

great! Is that observed or do you have a proof of this bound?
Did you try with inputs from [1] and [2]?

Note that it now exists some vector and correctly rounded implementations [3] and [4].

Paul

[1] https://gitlab.inria.fr/zimmerma/math_accuracy/-/blob/master/binary64/trig.wc
[2] https://gitlab.inria.fr/core-math/core-math/-/blob/master/src/binary64/sin/sin.wc
[3] https://www.arith2026.org/papers/Correctly%20rounded%20vector%20implementation%20of%20the%20exponential%20function%20in%20binary64%20arithmetic.pdf
[4] https://arxiv.org/pdf/2605.15547