Fiasco.OC interrupt handling

Daniel Waddington <[email protected]> Mon, 28 Jan 2013 09:55:38 -0800

Newsgroups	gmane.comp.micro-kernel.l4.devel
Organization	Samsung R&D
Message-ID	<[email protected]>

Hi,

I'm looking into the interrupt handling in Fiasco.OC r.40 (x86/amd64).  
Browsing the code, it appears that the IDT only gets set up on CPU 0 and 
therefore on a multicore platform all interrupt handling from the 
kernel's perspective is from core 0. Of course the user-level handlers 
themselves may be elsewhere.  Do I have this correct or am I 
misunderstanding?

Thanks,
Daniel

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