Re: Can you tell me function name that means 'Entry Point: 0x11000000' ?
Taeung <[email protected]>
| Newsgroups | gmane.comp.micro-kernel.l4.devel |
|---|---|
| Message-ID | <[email protected]> |
I've looked closely at the patch file you gave me . I've found that uart-imx.cpp and imx.cc could be applied by the patch file but there is some difference between your 'mem_layout-arm-imx.cpp' and my 'mem_layout-arm-imx.cpp'. So, I was able to not apply the patch file to my 'mem_layout-arm-imx.cpp'. How do you think about that ? Attached is my 'mem_layout-arm-imx.cpp'. I'm using a svn repository of which URL is "|http://svn.tudos.org/repos/oc/tudos/trunk/repomgr | perl - init http://svn.tudos.org/repos/oc/tudos fiasco l4re|". If you use other git repository, I want to tell me it's URL ,please . * Refer to > src/kernel/fiasco/src/kern/arm/bsp/imx/*uart-imx.cpp* src/l4/pkg/bootstrap/server/src/platform/*imx.cc* src/kernel/fiasco/src/kern/arm/bsp/imx/*mem_layout-arm-imx.cpp * - Taeung - On 03/23/2014 10:53 AM, Ahmed Ammar wrote: > Attached is the patch we use for the saber_sd's uart1: > > > > > On Mar 21, 2014, at 5:02 PM, Matthias Lange <[email protected]> wrote:? > >> Hi, >> >>> On 21 Mar 2014, at 11:33, Taeung <[email protected]> wrote: >>> >>> Hello, l4 hacker. >>> >>> >>> I'm trying to boot "Hello world / L4/ Fiasco" on Freescale i.MX6 Quad SABRE SD board(Cortex-A9, ARMv7). >>> >>> I'm using 'u-boot' and 'uImage'. >>> So, i build uimage by "make uimage E=hello ~...". >>> And i've try to booting it on Freescale i.MX6q_sabre_sd board. >>> But i did not it because stoped at "Starting kernel ..." !! >> Probably you selected the wrong UART, so the system is not printing something on the serial line. Make sure you have the right UART driver for your platform and make sure you have selected the right one. Usually there are more than one UARTs and only one is connected to you serial line. You can also check Linux to see which UART it uses. >> >>> MMC read: dev # 2, block # 2048, count 8192 ... 8192 blocks read: OK >>> ## Booting kernel from Legacy Image at 10800000 ... >>> Image Name: L4 Image #2 >>> Image Type: ARM Linux Kernel Image (uncompressed) >>> Data Size: 868352 Bytes = 848 kB >>> Load Address: 11000000 >>> Entry Point: 11000000 >>> Loading Kernel Image ... OK >>> OK >>> >>> Starting kernel ... >>> >>> >>> uimage's file name is "bootstrap_hello.uimage". >>> "bootstrap_hello.uimage" has information such as >>> "bootstrap_hello.uimage: u-boot legacy uImage, L4 Image #2, Linux/ARM, OS Kernel Image (Not compressed), 868352 bytes, >>> Thu Mar 20 13:14:42 2014, Load Address: 0x11000000, Entry Point: 0x11000000, Header CRC: 0xBEA251F3, Data CRC: 0xA0217B7D" >>> >>> I have a question. >>> >>> Can you tell me function name that means 'Entry Point: 0x11000000' ? >> In the uimage format the entry point is defined as the address where uboot should start, as the name implies, the execution of the image. >> >> >> Matthias. >> _______________________________________________ >> l4-hackers mailing list >> [email protected] >> http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers _______________________________________________ l4-hackers mailing list [email protected] http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers
mem_layout-arm-imx.cpp
(text/x-c++src, 2.3 KB)
INTERFACE [arm && imx]: //----------------------------------------------
EXTENSION class Mem_layout
{
public:
enum Phys_layout_imx : Address {
Flush_area_phys_base = 0xe0000000,
};
};
INTERFACE [arm && imx && imx21]: // ---------------------------------------
EXTENSION class Mem_layout
{
public:
enum Phys_layout_imx21 : Address {
Uart_phys_base = 0x1000a000,
Timer_phys_base = 0x10003000,
Pll_phys_base = 0x10027000,
Watchdog_phys_base = 0x10002000,
Pic_phys_base = 0x10040000,
};
};
INTERFACE [arm && imx && imx35]: // ---------------------------------------
EXTENSION class Mem_layout
{
public:
enum Phys_layout_imx35 : Address {
Uart_phys_base = 0x43f90000, // uart1
Timer_phys_base = 0x53f94000, // epit1
Watchdog_phys_base = 0x53fdc000, // wdog
Pic_phys_base = 0x68000000,
};
};
INTERFACE [arm && imx && imx51]: // ---------------------------------------
EXTENSION class Mem_layout
{
public:
enum Phys_layout_imx51 : Address {
Timer_phys_base = 0x73fac000, // epit1
Uart_phys_base = 0x73fbc000, // uart1
Watchdog_phys_base = 0x73f98000, // wdog1
Gic_dist_phys_base = 0xe0000000,
Gic_cpu_phys_base = 0xe0000000, // this is a fake address and not used
};
};
INTERFACE [arm && imx && imx53]: // ---------------------------------------
EXTENSION class Mem_layout
{
public:
enum Phys_layout_imx53 : Address {
Timer_phys_base = 0x53fac000, // epit1
Uart_phys_base = 0x53fbc000, // uart1
Watchdog_phys_base = 0x53f98000, // wdog1
Gic_dist_phys_base = 0x0fffc000,
Gic_cpu_phys_base = 0x0fffc000, // this is a fake address and not used
};
};
INTERFACE [arm && imx && imx6]: // -----------------------------------------
EXTENSION class Mem_layout
{
public:
enum Phys_layout_imx6 : Address {
Mp_scu_phys_base = 0x00a00000,
Gic_cpu_phys_base = 0x00a00100,
Gic_dist_phys_base = 0x00a01000,
L2cxx0_phys_base = 0x00a02000,
Uart1_phys_base = 0x02020000, // uart1
Watchdog_phys_base = 0x020bc000, // wdog1
Gpt_phys_base = 0x02098000,
Src_phys_base = 0x020d8000,
Uart2_phys_base = 0x021e8000, // uart2
Uart_phys_base = Uart2_phys_base,
};
};