Porting Fiasco.OC to RISC-V - Questions

Hi all,

I'm considering porting Fiasco.OC/L4Re to RISC-V architecture (for
both my research and GSoC). So, I started reading the documentation
and building the environment (For Fiasco.OC and RISC-V tools), and
QEMU (the emulator that I'll use initially) is running Hello World
example just fine.

After some reading, I wanted to start adding support for building L4Re
for RISC-V (is this a good start?), and I came up with some questions.

There are two variants of RISC-V ABI (32 and 64 bit) should I provide
both or just 64-bit version?

What are the minimal packages and/or Fiasco.OC system components that
need to be implemented to get Hello World working? Please correct me
if the following L4Re list is not right (contains more than needed, or
lack others):

"bootstrap, sigma0, moe, Log, libc, libc_minimal, cxx_util, cxx_io,
cxx_base, cxx_io_kdebug,l4sys-direct, l4sys"

Some of the packages are architecture dependent which need some code
from other projects (like uclibc), should I add them all? FYI, newlib
has support for riscv, but uclibc doesn't, how can I make the build
system choose specific packages for the target architecture (riscv in
this case) and maybe neglect building others?

Any other feedback or comments are welcomed.


-- 
Hesham