Re: Question about memory management in L4 Fiasco O.C + L4re

Adam Lackorzynski <[email protected]> Tue, 28 Jul 2015 23:38:58 +0200

Newsgroups	gmane.comp.micro-kernel.l4.devel
Message-ID	<[email protected]>

Hi,

On Tue Jul 28, 2015 at 16:10:04 +0200, Mahdi Aichouch wrote:
> I have a question about the way Fiasco.OC handles IPC.
> 
> If we take a simple example of one thread in address space A that sends an
> array of characters to a second
> thread located in an address space B.
> Since such an array might be large and cannot be transferred using the
> registers.
> 
> How it is transferred to the second thread address space?
> 
> Is it at first allocated on the first thread stack, then copied by Fiasco
> kernel to
> the second thread address space?

We use UTCBs for that. A UTCB is a dedicated memory region that each
thread has. Threads copy their IPC payload into their UTCB and the
kernel then copies the content to the receiver's UTCB.




Adam
-- 
Adam                 [email protected]
  Lackorzynski         http://os.inf.tu-dresden.de/~adam/