Problem when testing the "ex_isr" example on an ARMv7 Cortex-A9 based board.

Hello,

I tried to run the "ex_isr" example on a Freescale i.MX6 Quad Cortex A9
 Sabre SD board.

And I got an error saying: "Binding IRQ1 to the ICU failed".

Does someone has an idea of what might be wrong.

Below is the trace from the "ex_isr" example, followed by my globalconfig.h
file:

Thank you very much in advance.

Best regards,

Mahdi

L4 Bootstrapper
  Build: #53 Thu Nov 12 11:18:21 CET 2015, 4.8.3 20140320 (prerelease)
  Scanning up to 1024 MB RAM, starting at offset 32MB
  Memory size is 1024MB (10000000 - 4fffffff)
  RAM: 0000000010000000 - 000000004fffffff: 1048576kB
  Total RAM: 1024MB
  Scanning fiasco
  Scanning sigma0
  Scanning moe
  Moving up to 5 modules behind 11100000
  moving module 02 { 110b4000-110ed63f } -> { 111a4000-111dd63f } [235072]
  moving module 01 { 110aa000-110b338b } -> { 1119a000-111a338b } [37772]
  moving module 00 { 11044000-110a97cb } -> { 11134000-111997cb } [415692]
  moving module 04 { 1102a000-11043597 } -> { 1111a000-11133597 } [103832]
  moving module 03 { 11010000-11029473 } -> { 11100000-11119473 } [103540]
  Loading fiasco
  Loading sigma0
  Loading moe
  find kernel info page...
  found kernel info page at 0x10002000
Regions of list 'regions'
    [ 10000000,  100000e7] {       e8} Root   mbi_rt
    [ 10001000,  10001aff] {      b00} Kern   fiasco
    [ 10002000,  10072fff] {    71000} Kern   fiasco
    [ 10090000,  10096edf] {     6ee0} Sigma0 sigma0
    [ 10098000,  1009e177] {     6178} Sigma0 sigma0
    [ 10140000,  10171d77] {    31d78} Root   moe
    [ 10178000,  101934ab] {    1b4ac} Root   moe
    [ 11000000,  1100f4ff] {     f500} Boot   bootstrap
    [ 11100000,  11133fff] {    34000} Root   Module
  API Version: (87) experimental
  Sigma0 config    ip:10090100 sp:00000000
  Roottask config  ip:10140260 sp:00000000
  Starting kernel fiasco at 100012c8
Hello from Startup::stage2
Per_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8)
Number of IRQs available at this GIC: 160
FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p:
dbl/sngl
L2: ID=410000c7 Type=9e340340 Aux=32070000 WMask=ffff S=0
L2: Type L2C-310 Size = 1024kB  Ways=16 Waysize=64
SERIAL ESC: allocated IRQ 58 for serial uart
Not using serial hack in slow timer handler.
Welcome to Fiasco.OC (arm)!
L4/Fiasco.OC arm microkernel (C) 1998-2013 TU Dresden
Rev: rexported compiled with gcc 4.8.3 for i.MX6    []
Build: #192 Tue Nov 10 18:06:43 CET 2015

Per_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8)

KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000
Allocate 2504 bytes (2KB) for CPU[4] local storage (offset=1187af0,
0xf11ea000-0xf11ea9c8)
Number of CPUs: 4
Calibrating timer loop... Per_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8)
done.

KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000
Allocate 2504 bytes (2KB) for CPU[1] local storage (offset=1189af0,
0xf11ec000-0xf11ec9c8)
MDB: use page size: 20
MDB: use page size: 12
SIGMA0: Hello!
  KIP @ 10002000
  allocated 4KB for maintenance structures
SIGMA0: Dump of all resource maps
RAM:------------------------
[4:10000000;10000fff]
[0:10073000;1008ffff]
[0:10097000;10097fff]
[0:1009f000;1013ffff]
[4:10140000;10171fff]
[0:10172000;10177fff]
[4:10178000;10193fff]
[0:10194000;110fffff]
[4:11100000;11133fff]
[0:11134000;4effffff]
IOMEM:----------------------
[0:0;fffffff]
[0:50000000;ffffffff]
MOE: Hello world
FPU1: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p:
dbl/sngl
MPer_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8)
O
KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000
E: fCache config: ON
ouAllocate 2504 bytes (2KB) for CPU[2] local storage (offset=1140af0,
0xf11a3000-0xf11a39c8)
nd ID_PFR[01]:  00001231 000000111031156 ID_[DA]FR0: 00010444 00000000
 KID_MMFR[04]: 00100103 20000000 01230000 00102111
ByCPU[1]: goes to idle loop
te free memory
MOE: found RAM from 10000000 to 4f000000
MOE: allocated 1008 KByte for the page array @0x10194000
MOE: virtual user address space [0-bfffffff]
MOE: rom name space cap -> [C:501000]
  BOOTFS: [11100000-11119474] [C:503000] l4re
  BOOTFS: [1111a000-11133598] [C:504000] ex_isr
MOE: cmdline: moe --init=rom/ex_isr
MOE: Starting: rom/ex_isFPU2: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9,
i: 41, t: hard, p: dbl/sngl
rPer_cpu_data_alloc: (orig: 0xf0062510-0xf0062ed8)

Cache config: ON

KERNEL: Warning: Buddy::alloc: Size mismatch: 9c8 v 1000
ID_PFR[01]:  00001231 00000011M ID_[DA]FR0: 00010444 00000000
OID_MMFR[04]: 00100103 20000000 01230000 00102111
EAllocate 2504 bytes (2KB) for CPU[3] local storage (offset=1144af0,
0xf11a7000-0xf11a79c8)
: lCPU[2]: goes to idle loop
oading 'rom/ex_isr'
Binding IRQ1 to the ICU failed
MOE: task 270000679 exited with 1
FPU3: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard, p:
dbl/sngl
Cache config: ON
ID_PFR[01]:  00001231 00000011 ID_[DA]FR0: 00010444 00000000
ID_MMFR[04]: 00100103 20000000 01230000 00102111
CPU[3]: goes to idle loop




/*
 *
 * Automatically generated file; DO NOT EDIT.
 * Fiasco configuration
 *
 */
#define CONFIG_PERF_CNT 1
#define CONFIG_BIT32 1
#define CONFIG_MP_MAX_CPUS 4
#define CONFIG_EXPERIMENTAL 1
#define CONFIG_ARM_CORTEX_A9 1
#define CONFIG_ARM_CACHE_L2CXX0 1
#define CONFIG_CAN_ARM_CACHE_L2CXX0 1
#define CONFIG_ABI "vf"
#define CONFIG_CXX "g++"
#define CONFIG_LABEL ""
#define CONFIG_CAN_ARM_CPU_CORTEX_A9 1
#define CONFIG_ARM_ENABLE_SWP 1
#define CONFIG_ARM_V7 1
#define CONFIG_ARM 1
#define CONFIG_JDB 1
#define CONFIG_FPU 1
#define CONFIG_BSP_NAME "imx"
#define CONFIG_SCHED_FIXED_PRIO 1
#define CONFIG_CONTEXT_4K 1
#define CONFIG_HOST_CC "gcc"
#define CONFIG_MP 1
#define CONFIG_ABI_VF 1
#define CONFIG_NO_FRAME_PTR 1
#define CONFIG_ARM_V6PLUS 1
#define CONFIG_WARN_ANY 1
#define CONFIG_INLINE 1
#define CONFIG_SERIAL 1
#define CONFIG_PF_IMX_UART_NR 1
#define CONFIG_PF_IMX_UART_NR_1 1
#define CONFIG_PF_ARM_MP_CAPABLE 1
#define CONFIG_PF_IMX_RAM_PHYS_BASE 0x10000000
#define CONFIG_PF_IMX_6 1
#define CONFIG_XARCH "arm"
#define CONFIG_CC "gcc"
#define CONFIG_HOST_CXX "g++"
#define CONFIG_ARM_CPU_ERRATA 1
#define CONFIG_PF_IMX 1
#define CONFIG_WARN_LEVEL 2
#define CONFIG_VIRT_OBJ_SPACE 1
#define CONFIG_ARM_EM_STD 1

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