Re: Questions about Fiasco.OC scheduler and L4Linux
Marc CHALAND <[email protected]>
| Newsgroups | gmane.comp.micro-kernel.l4.devel |
|---|---|
| Message-ID | <CAHxfmfBsj-wemQcbkDrpGdz6LVD-1gGE3W-pmEBd3MC0e=DykQ@mail.gmail.com> |
Hi, 2017-03-22 23:45 GMT+01:00 Adam Lackorzynski <[email protected]>: > > Basically the vCPU model is an asynchronous execution model, that is > very similar to an actual CPU. I.e. you have vCPU that executes code and > that has an entry vector that is being jumped to whenever the vCPU shall > get an event (both asynchronous interrupts and synchronous exceptions). > To prevent diverting to the entry code there's a virtual interrupt flag, > i.e. if virtual interrupts are off, no message/interrupt will be posted. > Based on that multi-threading in the vCPU is implemented, i.e. some > timer triggers an interrupts, which in turn triggers some scheduling > code running in the vCPU which in turn does some stack switching. > You can also look into this paper > http://os.inf.tu-dresden.de/papers_ps/rtlws2010_genericvirt.pdf So, in that case, I have to implement my own scheduler to run it into one vCPU ? We don't have the code of the old scheduler. > I'm sure you've heard e.g. about Intel VT, or ARM's Virtualization > Extensions. Those are CPU features that basically allow you to > efficiently(!) execute OS kernels deprivileged, by providing another > layer of address translation and proper CPU exception handling. OSs > need to integrate those mechanism to run unmodified guest kernels. > In L4Re this is also mapped to a vCPU which however has more state. > The virtual platform is provided by a VMM component. > OK, I will have a look at that. Thank you for your answers. Regards Marc _______________________________________________ l4-hackers mailing list [email protected] http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers