Re: Booting L4Re on the CI20: Panic in sigma0

Sarah Hoffmann <[email protected]> Fri, 14 Jul 2017 17:39:15 +0200
Newsgroups	gmane.comp.micro-kernel.l4.devel
Message-ID	<[email protected]>
Hi Paul,

> 
> pkg/l4re-core/sigma0/server/src/ARCH-mips/crt0.S
> 
> This is what it looks like:
> 
> __start:
>         .cpload $25 /* load GP */
>         SETUP_GPX64($25, $0)
>         PTR_LA  $29, crt0_stack_high
>         PTR_LA  $25, init
>         PTR_SUBU  $29, (NARGSAVE * SZREG)
>         jalr $25
>           nop
> 
> The problem here is that the .cpload directive (operating on t9/$25) doesn't 
> have a known value of t9 to work with, it would seem. Consequently, the 
> calculations in the generated code work with a value that isn't initialised.

This suspiciously looks like a compiler issue. I would .cpload expect to
translate to a nop on mips32r2 without PIC. We generally use the
compilers provided by Imagination(*). The Debian GCC might do things
slightly differently, I need to check that again. Making the code work
with the official GCC is on our list, although not very high at the
moment. If you can switch to the Imgtec GCC for the moment, this might
save you some headache.

(*)
http://community.imgtec.com/developers/mips/tools/codescape-mips-sdk/download-codescape-mips-sdk-essentials/

> And that is then the end of output. Maybe I've stumbled across a difference in 
> the way the compilers work here. I'm using the mipsel-linux-gnu cross-
> compilers in Debian unstable, whereas I imagine that the people who ported the 
> code to MIPS used proprietary toolchains with different characteristics.
> 
> Anyway, I guess I'll investigate other places where this might be occurring 
> and hopefully get the "hello" program to do its thing.

It won't be that easy I'm afraid. Last time we tried the board, we found
that the CI20 has a crippled instruction set. In particular, it does not
support the rdhwr instruction which L4Re user programs use to clean
caches. The easiest way to work around this issue by emulating the
instruction in Fiasco. There is already some code for catching rdhwr.
Look for "ENTRY reserved_insn" in src/kern/mips/exception.S. Somebody
'just' needs to add support for reading the cache configuration values.

Kind regards

Sarah

-- 
Sarah Hoffmann, [email protected]

Kernkonzept GmbH, Dresden, Germany
https://kernkonzept.com/

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