Re: Booting L4Re on the CI20: Panic in sigma0
Paul Boddie <[email protected]>
| Newsgroups | gmane.comp.micro-kernel.l4.devel |
|---|---|
| Message-ID | <[email protected]> |
On Tuesday 18. July 2017 08.58.14 Sarah Hoffmann wrote: > > There is a bug in the Fiasco where it sends the wrong message size. > Please apply the attached patch to Fiasco. Afterwards you should get > more useful error messages in your L4 applications when it throws > exceptions. Yes, this fixes the recurring failure to handle the page fault successfully. Thanks for sending this! [...] > An address error generally means that you are trying to access a bad > address (which would be the case with the PFA given above). This is > different from a normal page fault, which corresponds to TLB exceptions. > That is why sigma0 is not involved. Right. I appreciate the clarification here. > Exceptions are directly sent to the exception handler which in a > standard L4 application is the thread started first (l4re-kernel thread) > or, if that one fails, the launcher (moe in your case). Yes, this is what I might have expected. [...] > The t9 issue is a likely cause. There are a couple of places where > .cpload is used. I found another location where t9 is not initialised: pkg/l4re-core/l4re_kernel/server/src/ARCH-mips/loader_mips.S I had actually seen this, but I guess I was distracted too much with the other problems to realise that it needed changing. So, I applied the Fiasco patch and then looked at the above file, checking the objdump output for the l4re binary. With the patch applied, the page fault did not occur endlessly, and with a change to the above file similar to those already made for sigma0 and moe, it appears that the page fault is eliminated completely. As a consequence, the "hello" example now runs, finally! I have attached a few patches required to make this happen in my 32-bit Intel, Debian-based mipsel-linux-gnu development environment: ci20-gcc-cpload.diff Initialises t9 for .cpload ci20-gcc-debian.diff Uses the mipsel-linux-gnu toolchain prefix ci20-rdhwr.diff Implements rdhwr SYNCI_Step handling ci20-uart0.diff Uses the UART0 connection to work around UART4 problems no-at.diff A missing definition (mentioned previously on this list) The rdhwr patch could probably be improved, and I think there are places in the affected file where common code could be consolidated a bit more. I appreciate the help and guidance you have provided in getting me to this point, and I hope now to try and test the drivers that I had written in advance of getting the examples working. Thanks once again, Paul _______________________________________________ l4-hackers mailing list [email protected] http://os.inf.tu-dresden.de/mailman/listinfo/l4-hackers
ci20-gcc-cpload.diff
(text/x-patch, 1.5 KB)
Index: l4/pkg/l4re-core/l4re_kernel/server/src/ARCH-mips/loader_mips.S =================================================================== --- l4/pkg/l4re-core/l4re_kernel/server/src/ARCH-mips/loader_mips.S (revision 72) +++ l4/pkg/l4re-core/l4re_kernel/server/src/ARCH-mips/loader_mips.S (working copy) @@ -1,7 +1,11 @@ #include <sys/regdef.h> #include <sys/asm.h> +.set noreorder LEAF(loader_thread) + lui $25, %hi(__real_loader_thread) + ori $25, $25, %lo(__real_loader_thread) +__real_loader_thread: .cpload $25 SETUP_GPX64($25, $0) PTR_LA $25, loader_thread_c Index: l4/pkg/l4re-core/moe/server/src/ARCH-mips/crt0.S =================================================================== --- l4/pkg/l4re-core/moe/server/src/ARCH-mips/crt0.S (revision 72) +++ l4/pkg/l4re-core/moe/server/src/ARCH-mips/crt0.S (working copy) @@ -21,6 +21,9 @@ .globl _real_start .set noreorder _real_start: + lui $25, %hi(__real_start) + ori $25, $25, %lo(__real_start) +__real_start: .cpload $25 /* load gp */ SETUP_GPX64($25, $0) PTR_LA $29, _stack_top Index: l4/pkg/l4re-core/sigma0/server/src/ARCH-mips/crt0.S =================================================================== --- l4/pkg/l4re-core/sigma0/server/src/ARCH-mips/crt0.S (revision 72) +++ l4/pkg/l4re-core/sigma0/server/src/ARCH-mips/crt0.S (working copy) @@ -14,6 +14,9 @@ .globl __start .set noreorder __start: + lui $25, %hi(__realstart) + ori $25, $25, %lo(__realstart) +__realstart: .cpload $25 /* load GP */ SETUP_GPX64($25, $0) PTR_LA $29, crt0_stack_high
ci20-gcc-debian.diff
(text/x-patch, 904 B)
Index: kernel/fiasco/src/Makeconf.mips =================================================================== --- kernel/fiasco/src/Makeconf.mips (revision 72) +++ kernel/fiasco/src/Makeconf.mips (working copy) @@ -4,7 +4,7 @@ BITS-$(CONFIG_BIT64) = 64 BITS = $(BITS-y) -CROSS_COMPILE-32 ?= mips-linux- +CROSS_COMPILE-32 ?= mipsel-linux-gnu- CROSS_COMPILE-64 ?= mips64el-linux-gnuabi64- CROSS_COMPILE ?= $(CROSS_COMPILE-$(BITS)) Index: l4/mk/arch/Makeconf.mips =================================================================== --- l4/mk/arch/Makeconf.mips (revision 72) +++ l4/mk/arch/Makeconf.mips (working copy) @@ -1,4 +1,4 @@ -CROSS_COMPILE_mips = mips-linux- +CROSS_COMPILE_mips = mipsel-linux-gnu- ELF_BINARY_TYPE_mips_32 = elf32 ELF_BINARY_TYPE_mips_64 = elf64 LD_EMULATION_CHOICE_mips = $(ELF_BINARY_TYPE_mips_$(CPU_ABI))ltsmip
ci20-rdhwr.diff
(text/x-patch, 3.7 KB)
Index: kernel/fiasco/src/kern/mips/exception.S =================================================================== --- kernel/fiasco/src/kern/mips/exception.S (revision 72) +++ kernel/fiasco/src/kern/mips/exception.S (working copy) @@ -357,40 +357,65 @@ ENTRY reserved_insn # NOTE. currently does not work for guest reserved insn redirect - # Handle emulation of rdhwr instruction for TLS (ULR) + # Handle emulation of rdhwr instruction for TLS (ULR) and SYNCI_Step ASM_MFC0 k0, CP0_EPC - lw k1, 0(k0) # load instruction - li k0, 0x7c00e83b - li $at, 0xffe0ffff - and $at, $at, k1 # check for rdhwr .., $29 - bne $at, k0, 1f # do normal slowtrap entry if not rdhwr .., $29 - ext k0, k1, 16, 5 # extract target register number + lw k1, 0(k0) # load instruction + # Test for rdhwr .., $29 (ULR) + + # SPECIAL3_____........29_____RDHWR. + li k0, 0x7c00e83b # 01111100000000001110100000111011 + li $at, 0xffe0ffff # mask for rdhwr test + and $at, $at, k1 # check for rdhwr .., $29 + bne $at, k0, 5f # test for rdhwr .., $1 if not rdhwr .., $29 + ext k0, k1, 16, 5 # extract target register number + + # Handle TLS (ULR) access + move $at, sp ins $at, zero, 0, THREAD_BLOCK_SHIFT # TCB addr in $at + ASM_L $at, OFS__THREAD__ULR($at) + b 6f + nop + + # Test for rdhwr .., $1 (SYNCI_Step) +5: + # SPECIAL3_____.........1_____RDHWR. + li k0, 0x7c00083b # 01111100000000000000100000111011 + li $at, 0xffe0ffff # mask for rdhwr test + and $at, $at, k1 # check for rdhwr .., $1 + bne $at, k0, 1f # do normal slowtrap entry if not rdhwr .., $1 + ext k0, k1, 16, 5 # extract target register number + + # Handle SYNCI_Step access + + ASM_MFC0 k1, CP0_CONFIG, 1 + ext k1, k1, 19, 3 # CONFIG1<21:19> = IL<2:0> = (log2(line size) - 1) or 0 + beqz k1, 6f # exit with zero value if line size is zero + li $at, 0 + li $at, 2 + sllv $at, $at, k1 # 2 << (log2(line size) - 1) == line size + + # Jump to the register loading instruction +6: sll k0, k0, 3 # 32 insn bundles (2 insns) one for each target ASM_LA k1, 2f # register at 2f ASM_ADDU k0, k1, k0 # calculate the address of the target register load - lw k1, TS_STATUS(CALL_FRAME_SIZE)(sp) - mtc0 k1, CP0_STATUS # restore CP0 Status as the entry code modified it - ASM_MFC0 k1, CP0_EPC # skip the rdhwr insn - ASM_ADDIU k1, k1, 4 - ASM_MTC0 k1, CP0_EPC jr k0 # jump to the register loading code ehb # prepare for eret - # Load the target register with the ULR value + # Load the target register with the required value from $at # we have 32 instruction bundles that load the - # target register and brnach to the exit code + # target register and branch to the exit code 2: b 3f nop b 4f - ASM_L $at, OFS__THREAD__ULR($at) + nop .irp reg, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25 b 3f - ASM_L $\reg, OFS__THREAD__ULR($at) + move $\reg, $at .endr b 3f nop @@ -397,18 +422,25 @@ b 3f nop b 3f - ASM_L $28, OFS__THREAD__ULR($at) + move $28, $at b 3f # ignore store to sp (r29) nop b 3f - ASM_L $30, OFS__THREAD__ULR($at) + move $30, $at nop - ASM_L $31, OFS__THREAD__ULR($at) + move $31, $at -3: load_reg 1, 29 -4: load_reg 29, 29 +3: load_reg 1, 29 +4: /* no need to restore k0, k1 here as this must never happen * from guest mit with VZ */ + lw k1, TS_STATUS(CALL_FRAME_SIZE)(sp) + mtc0 k1, CP0_STATUS # restore CP0 Status as the entry code modified it + ASM_MFC0 k1, CP0_EPC # skip the rdhwr insn + ASM_ADDIU k1, k1, 4 + ASM_MTC0 k1, CP0_EPC + + load_reg 29, 29 eret 1: # do normal slowtrap entry
ci20-uart0.diff
(text/x-patch, 811 B)
Index: l4/pkg/bootstrap/server/src/platform/ci20.cc
===================================================================
--- l4/pkg/bootstrap/server/src/platform/ci20.cc (revision 72)
+++ l4/pkg/bootstrap/server/src/platform/ci20.cc (working copy)
@@ -27,9 +27,11 @@
unsigned long uart_base;
kuart.base_baud = 3000000;
- kuart.base_address = 0x10034000; // UART4
+ // kuart.base_address = 0x10034000; // UART4
+ kuart.base_address = 0x10030000; // UART0 for CI20 primary expansion connector
kuart.reg_shift = 2;
- kuart.irqno = 34;
+ // kuart.irqno = 34;
+ kuart.irqno = 51; // UART0: 32 + 19
static L4::Uart_16550 _uart(kuart.base_baud, 0, 0, 0, 0x10 /* FCR UME */);
static L4::Io_register_block_mmio r(kuart.base_address + Mips::KSEG1,
no-at.diff
(text/x-patch, 375 B)
Index: l4/tool/gendep/syscall.c =================================================================== --- l4/tool/gendep/syscall.c (revision 72) +++ l4/tool/gendep/syscall.c (working copy) @@ -17,6 +17,7 @@ #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> +#define __ARCH_WANT_SYSCALL_NO_AT #include <unistd.h> #include <sys/syscall.h> #include <unistd.h>