Re: Basic support for HiKey960 & SMP question

Martin Decky <[email protected]> Mon, 20 Sep 2021 16:44:11 +0000

Newsgroups	gmane.comp.micro-kernel.l4.devel
Message-ID	<[email protected]>

Dear Adam,

thanks for your reply!
 
> I'm not sure about the QEMU part (works fine for me)

For the record, this is what I did:

(1) Start with the vanilla base 21.07.0 snapshot.

(2) Manually update the respective components (i.e. src/fiasco, src/l4/mk,
src/l4/pkg/bootstrap, etc.) from the respective GitHub repositories. Maybe
I've missed something, but I was unable to find any integration repository
that would just point to the other repos as submodules or something in that
style. And I don't know where is the upstream of things like bin/setup.d and
alike.

(3) Compile the resulting composition for arm64-virt-el2. The compilation
finishes OK.

(4) Run the compilation output in QEMU. See the log attached. The UART still
echoes the input, thus I believe the kernel does not crash, but there is no
forward progress.

I am sure that I would be able to find and fix the problem eventually. But I
simply prefer a working baseline before doing some development and therefore
I have stuck to the vanilla snapshot :)

> but on the HiKey my
> guess would be that the cache on those cores is not enabled?
> Could you check this?

Like I have written before, I have tried to confirm that the memory is
mapped with the correct attributes. The JTAG debugger reports that the
memory region where _tramp_mp_spinlock is located in a memory region that is
inner shareable, inner write-back, outer write-back, read allocate, write
allocate, non-transient.

I have also tried to confirm this from the code:

(a) MAIR_EL2 is set to 0x00ff4400. Which means that the attribute index 2
represents normal cacheable memory.

(b) TCR_EL2 is set to 0x80853510. Which means that the memory is inner
shareable, normal outer write-back read allocate write allocate, normal
inner write-back read allocate write allocate.

(c) SCTLR_EL2 is set to 0x30c51835. Which means that the instruction cache,
the data cache and the memory translation are enabled.

(d) I must say that the code in kern/arm/paging-arm.cpp is extremely hard to
understand and analyze (compared to most kernels I've ever seen), not just
because it is plagued by non-symbolic constants. But I still believe that
the value of 0x008 on the line 835 translates to using the attribute index 2
(see above).

Am I missing something?


Best regards

Martin Decky

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l4re-upstream.log (application/octet-stream, 2.8 KB)

$ qemu-system-aarch64 -nographic -M virt,virtualization=on -cpu cortex-a57 -smp 4 -m 1024 -kernel ./obj/l4/arm64/images/bootstrap_hello.uimage 

L4 Bootstrapper
  Build: #2 Mon Sep 20 17:27:51 CEST 2021, 11.1.0
  Scanning up to 1024 MB RAM, starting at offset 32MB
  Memory size is 1024MB (40000000 - 7fffffff)
  RAM: 0000000040000000 - 000000007fffffff: 1048576kB
  Total RAM: 1024MB
  Scanning fiasco
  Scanning sigma0
  Scanning moe
  Moving up to 5 modules behind 41100000
  moving module 04 { 410e7000-4110b79f } -> { 411d3000-411f779f } [149408]
  moving module 03 { 410cb000-410e6b1f } -> { 411b7000-411d2b1f } [113440]
  moving module 02 { 41099000-410ca217 } -> { 41185000-411b6217 } [201240]
  moving module 01 { 41093000-41098b47 } -> { 4117f000-41184b47 } [23368]
  moving module 00 { 41014000-41092107 } -> { 41100000-4117e107 } [516360]
  Loading fiasco
  Loading sigma0
  Loading moe
  find kernel info page...
  found kernel info page (via ELF) at 40003000
Regions of list 'regions'
    [ 40000000,  40000fff] {     1000} Root   mbi_rt
    [ 40001000,  4008efff] {    8e000} Kern   fiasco
    [ 40100000,  4010a46f] {     a470} Sigma0 sigma0
    [ 40140000,  40170adb] {    30adc} Root   moe
    [ 40171ae0,  4017cd0f] {     b230} Root   moe
    [ 41000000,  41012a03] {    12a04} Boot   bootstrap
    [ 41013200,  410135d4] {      3d5} Boot   modinfo
    [ 411b7000,  411f779f] {    407a0} Root   Module
  found kernel options (via ELF) at 40004000
  Sigma0 config    ip:40100474 sp:00000000
  Roottask config  ip:401414f4 sp:00000000
  Starting kernel fiasco at 40001670
Hello from Startup::stage2
GICv2
Number of IRQs available at this GIC: 288
Detecting PSCI ...
Detected PSCI v0.2
PSCI: TOS: Not present or not required.
FPU: Initialize
ARM generic timer: freq=62500000 interval=62500 cnt=5302525
SERIAL ESC: allocated IRQ 33 for serial uart
Not using serial hack in slow timer handler.
Welcome to L4/Fiasco.OC!
L4/Fiasco.OC microkernel on arm
Rev: a4d65e72-dirty compiled with gcc 11.1.0 for QEMU Virtual Platform    []
Build: #1 Mon Sep 20 17:23:48 CEST 2021

Allocate ARM PPI 25 to virtual 0
Allocate ARM PPI 27 to virtual 1
Calibrating timer loop... Allocate ARM PPI 25 to virtual 0
Allocate ARM PPI 25 to virtual 0
Allocate ARM PPI 25 to virtual 0
Allocate ARM PPI 27 to virtual 1
Allocate ARM PPI 27 to virtual 1
Allocate ARM PPI 27 to virtual 1
Cache config: ON
Cache config: ON
Cache config: ON
ID_PFR[01]:  00000222 00000000ID_PFR[01]:  00000222 00000000 ID_[DA]FR0: 10305106 00000000
ID_PFR[01]:  00000222 00000000done.
ID_MMFR[04]: 00001124 00000000 00000000 00000000
 ID_[DA]FR0: 10305106 00000000
 ID_[DA]FR0: 10305106 00000000
ID_MMFR[04]: 00001124 00000000 00000000 00000000
ID_MMFR[04]: 00001124 00000000 00000000 00000000
MDB: use page size: 30
MDB: use page size: 21
MDB: use page size: 12

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