Re: Basic support for HiKey960 & SMP question

Hi Martin!

On 9/17/21 15:05, Martin Decky wrote:
> In a nutshell, the additional 3 little cores (A53) are woken up correctly
> using the PSCI call (I am not tackling the 4 big A73 cores yet), but the
> Fiasco code livelocks in the loop around the STXR instruction in
> src/kern/arm/64/tramp-mp.S [3]. The STXR instruction always reports that the
> exclusive access to the _tramp_mp_spinlock failed despite no other accesses
> to the spinlock happened (confirmed using a JTAG debugger).

Does the behavior change if you enable only 2 CPUs in your Fiasco config 
so that you have the BSP and only one AP?

Jakub