Re: clarification on explicit preemption points in Fiasco IPC
"bahadir balban" <[email protected]>
| Newsgroups | gmane.comp.micro-kernel.l4.l4ka.general |
|---|---|
| Message-ID | <[email protected]> |
> From: Sergio Ruocco <[email protected]> > Subject: clarification on explicit preemption points in Fiasco IPC > As far as I know, Fiasco is entirely preemptable. Then why sprinkling > the IPC path with Enable IRQs/NOP NOP/Disable IRQs ? > > Thanks in advance, > > Sergio I have neither seen Fiasco code nor have any prior experience with it; but, my guess would be that during the IPC critical path the irqs are kept disabled. So, possibly to reduce latency irqs are given a chance to run at safe points within this path. If you expect that they're already enabled during that path, then confirm by checking that sti() and cli() are no-ops as well. They *must* be no-ops, otherwise particularly cli() would incorrectly disable the irqs. Thanks, Bahadir