Some remarks on Pistachio.

Hi,

a few weeks ago, i started to study your pistachio kernel at the same 
time the Intel Architecture. As my knowledge of both is growing (a 
little at the time), i have some remarks:

1 - In the file "/kernel/src/arch/x86/mmu.h" : Calling the 
"flush_tlb(bool global)" function with "global" set to true will 
activate the global pages even if they are not. In fact, this function 
suppose that if "global" is set to true, the global page mechanism is 
active.

2 - In the file "/kernel/src/arch/x86/x32/segdesc.h" : In lines 80 and 
102, it is more logical to use 0xf in place of 0xff as the limit_high 
field is only 4 bits.

3 - In the file "/kernel/src/arch/x86/segdesc.h" : In the 
"x86_descreg_t", why do you use the member 
"pad[sizeof(word_t)-sizeof(u16_t)]" in the union ? The GDTR and IDTR 
registers are 48 bits (address + limit) and the TR and LDTR registers 
are only 16 bits (selector) even if they are internally larger (the 
hidden part, only accessible by processor).

Willy.