RE:

Hi Inti,

How TCBs are managed in the kernel is essentially a matter of implementation.  The current L4Ka implementation offers two different options that can be chosen from at build time through the menu: a virtual linear array or a normal array. The former is very efficient and easy to use in terms of retrieving a TCB, but has impact on virtual address space and TLB entries; so in case this is a problem for a certain architecture or scenario, the second option is a viable option.

Best,
-Jan


--
Dr.-Ing. Jan Stoess
KIT/UKa System Architecture Group
Phone: +49 (721) 608 4056
Fax: +49 (721) 608 7664
http://os.ibds.kit.edu/stoess

From: [email protected] [mailto:[email protected]] On Behalf Of Inti Yulien Gonzalez Herrera
Sent: Thursday, November 25, 2010 19:28
To: [email protected]
Subject:

Hi:
I am trying to understand how kernel memory is handled in L4. I read a few articles but i can not understand how to obtain space for processor structures for paging. The UTCB concept is more comprensible to me. However how are stored TCB? Not UTCB.
On x86 processors, how L4 handles page directories and page tables for every address space?
How L4 keeps them?
I read for instance:
"On microkernel construction"
"User-Level Management of Kernel Memory"

Thank,
Inti

________________________________
Universidad Central "Marta Abreu" de Las Villas. http://www.uclv.edu.cu