Re: FPGA encode stages flow diagram

> I create diagram of encoder process. Using it i create implementation of
> encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing
> stages?

So, you're missing motion estimation/motion compensation/macro block 
mode decision/skip decision. These are not required for an encoder, of 
course, but are pretty important for getting compression that is at all 
reasonable. Even just the "NOMV" modes (where the motion vector is 
always (0,0)) are already a big improvement over all-INTRA. IIRC, this 
is the route the Elphel 333 FPGA encoder took. You're also missing the 
loop filter, though I guess if there's no motion compensation at all 
(not even NOMV), this isn't actually required, either.