Re: FPGA encode stages flow diagram

Good day!
in Theora spec wrote (page 18, paragraph "DCT Coe cients"):
"...Tokens are grouped in the stream by token index, not by the block they
originate from. This means that for each zig-zag index in turn, the tokens
with
that index from all the coded blocks are coded in coded block order. When
decoding, a current token index is maintained for each coded block. This
index
is advanced by the number of coe cients that are added to the block as each
token is decoded. After fully decoding all the tokens with token index ti ,
the
current token index of every coded block will be ti or greater...."


ok.
for example, my encoder produce only two blocks:
1) in first block (after DCT) i have
AC0=1;
AC(1..62)=0;
AC63=1;
so, after zig-zag + RLE  have tokens for
AC0=(0,1);
AC63=(62,1)

1) in first block (after DCT) i have
AC0=1;
AC1=1;
AC(2..62)=0;
AC63=1;
so, after zig-zag + RLE  have tokens for
AC0=(0,1);
AC1=(0,1);
AC63=(61,1)


Acording to paragraph "DCT Coe cients", encoder must pack coefficients by
token index (index = zig-zag number of coeff), ok i pack:
for index=0:   (0,1);(0,1);
...
..
for index=63: (62,1);(61,1)


what about tokens for index 1-61?

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