Re: FPGA encode stages flow diagram

Thank you Timothy!

Now i undestand how tokens are made from zig-zaged block. I redraw
stage-I in my blog http://developer-fpga.blogspot.com/, see diagram
https://lh4.googleusercontent.com/-wDLGljOWTCs/TY3ofIhqNzI/AAAAAAAAAp8/nvdCht-qjbc/s1600/stage1.a.jpg

 But i'm litle confused seen table 7.38 of Theora spec. How i
understand we use only 8 bit values in coder (for quantized
coefficient of block), but in table 7.38 is (for example token value =
22) i see tokenization of values more than 255? How it's possible?
Extrabits for token value=22 is 10 bits. This mean we can present
-512..+512 magnitude values for coeffs..... How it's possible? Ok. May
be this is why when DCTed our 8-bits values we at result have 16-bits
value out. Ok this is understand, but why realy thear are tokens  fo
10-bits value? (Is it  because we use quantization ?)

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