Re: [Gc] Fwd: Re: AArch64: Shareability domain for dmb st overly conservative (#11)

I agree that we should be using "dmb ish"/"dmb ishst" everywhere.  The
plain variants are theoretically slower, and should not be needed.  That
said, with limited experimentation, I have not yet found a processor
implementation for which it actually matters, though I have heard that they
exist.

Note that the "st"/"ishst" barriers are actually quite weak and, as the
libatomic_ops documentation states, usually not what you really want.  And
at this stage we should really move towards the C11 primitives anyway.

This all applies to both Aarch64 and Arm32.

Hans

On Sat, Oct 25, 2014 at 10:29 AM, Ivan Maidanski <ivmai-JGs/[email protected]> wrote:

> Forwarding to ML..
>
> From: Ivan Maidanski <ivmai-JGs/[email protected]>
> To: Yvan Roux <[email protected]>, Hans Boehm <[email protected]>
> CC: ivmai/libatomic_ops <[email protected]>,
> ivmai/libatomic_ops <
> reply+i-46004519-50324839f75648d459559128d780ac126d37fdde-460469-EymDizFzQUc@public.gmane.orgthub.com>,
> Boehm GC <[email protected]>
> Date: Thu, 23 Oct 2014 12:36:39 +0400
> Subject: Re: [libatomic_ops] AArch64: Shareability domain for dmb st
> overly conservative (#11)
>
>   Hi Yvan and Hans,
>
> Is the proposed change correct for ARM64 AO_nop_write? What's about 32-bit
> ARM?
>
> Thank you
>
> Thu, 16 Oct 2014 09:08:26 -0700 from stevecapperlinaro <
> notifications-9UaJU3cA/F/[email protected]>:
>
>   Hello,
> In src/atomic_ops/sysdeps/gcc/aarch64.h, we have the following code:
> __asm__ __volatile__("dmb st" : : : "memory");
>
> This will target the system domain and thus be overly conservative as the
> CPUs will occupy the inner shareable domain.
>
> Could this please be changed to:
> __asm__ __volatile__("dmb ishst" : : : "memory");
>
> That way the barriers will occupy the inner shareable domain.
>
> Thanks,
> Steve Capper
>
> —
>
>
>
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