Re: [Gc] Fwd: Re: AArch64: Shareability domain for dmb st overly conservative (#11)
Hans Boehm <[email protected]> Wed, 5 Nov 2014 10:16:26 -0800
| Newsgroups | gmane.comp.programming.garbage-collection.boehmgc |
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| Message-ID | <CAPUmR1Zv12yzsbmtFWcSAd_vxs4s=jgZWdTeBqpsoyKfVP134w@mail.gmail.com> |
I don't think a relaxed fence does anything. Memory_order_relaxed loads and stores require single-location coherence. The aarch64 spec guarantees that for ordinary memory operations. (So does arm32, though there is a common arm32 bug that violates it. It is unclear whether arm32 relaxed loads should be treated as acquire for that reason. But I don't think that concern applies to aarch64.) Hans On Wed, Nov 5, 2014 at 9:06 AM, Andrew Haley <[email protected]> wrote: > On 11/04/2014 09:28 AM, Yvan Roux wrote: > > To give a full picture of the __atomic_thread_fence builtin for > > AArch64, here is the generated code (by trunk) for each model: > > > > __ATOMIC_RELAXED -> nothing > > I'm pretty sure that is wrong. ATOMIC_RELAXED does imply single- > word coherence, AIUI. > > Andrew. > > _______________________________________________ bdwgc mailing list [email protected] https://lists.opendylan.org/mailman/listinfo/bdwgc