Deadline extended: 2006 Workshop on Memory Systems Performance & Correctness (MSPC 2006)

The submission deadline has been extended by nearly a month, to July 28.

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			   Call For Papers

2006 ACM SIGPLAN Workshop on Memory Systems Performance & Correctness
			     (MSPC 2006)
                    
		 October 22, 2006 - San Jose, CA, USA

		      Co-located with ASPLOS XII

		   http://www.cs.purdue.edu/MSPC06

MSPC focuses on improving the memory system performance and correctness of general-purpose programs. MSPC continues the successful series of MSP workshops held in 2002 (Berlin), 2004 (Washington, DC), and 2005 (Chicago). This multi-disciplinary workshop fosters collaboration among researchers in a range of fields including compilers, memory management, programming languages, architecture, operating systems, performance evaluation, and database systems.

Important dates:

* Abstract:         Monday July 24, 2006
* Paper submission: Friday July 28, 2006, at 11:59:59 PM Eastern time
* Notification:     September 8, 2006
* Final paper:      September 22, 2006

We solicit papers on all aspects of memory system performance and correctness. Areas of interest include but are not limited to the following topics:

* Analysis of memory systems performance (including power, bandwidth,
  and latency)
* Static and dynamic techniques for understanding and improving memory
  performance
* Hardware and software techniques for ensuring memory safety and
  detecting memory-related bugs (e.g., memory leaks, dangling
  pointers, out-of-bounds memory accesses, invalid C pointer
  arithmetic)
* Hardware memory models and their impact on software
* Specifications of programming language (and library) shared memory
  semantics
* Better shared-memory programming models (e.g., transactional memory)
* Data race detection and debugging of programs with (possibly
  intentional) data races
* Managed memory and garbage collection optimizations
* Memory hierarchy design for chip multiprocessors (CMPs)
* Pre-fetching and compression to improve memory system performance
* Code, data, or page placement to eliminate page faults and cache
  misses
* Memory system issues in embedded computers and tiny devices
* Impact of new storage technologies

Software, hardware, and hybrid approaches are encouraged.  In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.

Submission Guidelines: Full paper submissions should not exceed 10 pages in standard ACM SIGPLAN conference format. Papers should be submitted electronically through the workshop web site (www.cs.purdue.edu/MSPC06). Copies of accepted papers will be made available at the workshop and published in the ACM digital library. Submitted papers must not be simultaneously under review for any other conference or journal, and authors should point out any substantial overlap with their previously published or currently submitted work.

Organizing Committee

General chair:   Antony Hosking, Purdue U

Program chair:   Ali-Reza Adl-Tabatabai, Intel

Program committee

Emery Berger, U. Massachusetts, Amherst
Hans Boehm, HP Labs
Martin Burtscher, Cornell University
Barbara Chapman, U. Houston
David Chase, Sun Microsystems
Brad Chen, Intel
Amer Diwan, U. Colorado, Boulder
Cormac Flanagan, UC Santa Cruz
Thomas Gross, ETH Zürich
Dan Grossman, U. Washington
Glenn Reinman, UCLA
Qing Yi, UT San Antonio



--
Emery Berger
Assistant Professor
Dept. of Computer Science
University of Massachusetts, Amherst
www.cs.umass.edu/~emery