Re: Truly lock-free multi-processor card marking

Jason Evans wrote:
> I have searched in vain for several hours now, trying to find any 
> information for amd64/x86_64 about the minimum quantum that can be 
> written to without danger of the write being converted to 
> read-modify-write.  Any information, whether specific or general, is 
> much appreciated.


You are worried about an issue that hinges on the detailed specifics of 
how cache coherency is implemented.

That is an area in hot flux -- it's changing all the time and there are 
a lot of variations out there "in the wild".   So, you shouldn't expect 
any kind of simple answer, not even if you limit your attention to 
x86.   You are right that varying the memory overhead for the card bits 
can make a difference, but mistaken if you expect a reliable theory as 
to exactly how (other than wider is probably faster in multi-core 
environments -- probably).

Don't optimize prematurely but if you parameterize your code in the 
width and then prove it makes a difference -- then you've got a system 
specific tuning parameter.    I don't think you can do much better than 
try to pick some good defaults for that parameter -- and that probably 
requires tedious experimentation (c.f. "Don't optimize prematurely....").

-t



(by analogy, sometimes interpreter implementors find that randomly 
rewriting their "eval" procedure to better align on cache boundaries or 
better fit within a cache makes a huge difference in a controlled 
environment -- but there's no systematic "right way" fit eval for 
systems in general.)