CFP: MSPC 2008 (co-located with ASPLOS)

In addition to a nice program, we have an exciting panel discussion
planned, so we encourage everyone to sign up and participate.

MSPC 2008 - ACM SIGPLAN Workshop on Memory Systems Performance and  
Correctness
March 2, 2008, Seattle, Washington, USA
co-located with ASPLOS 2008
http://www.cs.umass.edu/~emery/MSPC08/

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** Panelists announced for MSPC's "The Next Solution" panel - see  
below. **

** REMINDER - EARLY-BIRD REGISTRATION DEADLINE IS FEBRUARY 11! **
http://research.microsoft.com/asplos08/registration.htm
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As CPUs rely increasingly on parallelism rather than frequency to
improve performance, the memory system emerges as the fundamental
barrier to continued improvement in system-level performance. Previous
tactics like increasing cache size and associativity become less and
less relevant in a world where NUMA memory behaviors and
inter-processor contention dominate application performance. MSPC is a
forum for exploring these emerging challenges. This multidisciplinary
workshop fosters collaboration among researchers in compilers,
programming languages, architecture, operating systems and adjacent
specialties. Remember to register for MSPC when you register for
ASPLOS!

Final Program

9:00 am - Welcome and Introduction
Emery Berger and Brad Chen

9:30 am - Programming Methodology
Session Chair: Emery Berger, University of Massachusetts Amherst

General and efficient locking without blocking
Yannis Smaragdakis, Anthony Kay, Reimer Behrends and Michal Young

Concurrency Control with Data Coloring
Luis Ceze, Christoph von Praun, Calin Cascaval, Pablo Montesinos and
Josep Torrellas

10:30 am - Break

11:00 am - Memory Systems for Parallel Hardware
Session Chair: Trevor Mudge, University of Michigan

The Potential for Variable-Granularity Access Tracking for Optimistic
Parallelism
Mihai Burcea, J. Gregory Steffan and Cristiana Amza

Reasoning about the ARM weakly consistent memory model
Nathan Chong and Samin Ishtiaq

IWannaBit!
Cliff Click

12:30 pm - Lunch

1:30 pm - Wild and Crazy Ideas Session

2:30 pm - Software Analysis
Session Chair: Cliff Click, Azul Systems

What can performance counters do for memory subsystem analysis?
Stephane Eranian

The Case for Simple, Visible Cache Coherency
Robert Kunz and Mark Horowitz

GC Assertions: Using the Garbage Collector to Check Heap Properties
Edward Aftandilian and Samuel Guyer

4:00 pm - Break

4:15 pm - Panel: The Next Solution
Session Chair: Bruce Jacob, University of Maryland

People have been complaining about the memory system for at least two
decades. As a result, industry and academia have explored numerous
solutions, in both software and hardware, at the technology level, the
channel level, and the system level. The applications folks have
expected big rewards from each solution, only to be disappointed at
just about every turn. One of the most recent examples is multicore
(one of many "indirect" solutions, marketed as not solving but
tolerating the memory system), which exacerbated the memory-bandwidth
problem instead of reducing it. Today, people still complain about the
memory system: if anything, the problem is commonly represented as
getting worse. So what is the next solution?

- Dave Resnick, Micron
- Hillery Hunter, IBM Watson
- Jim Larus, Microsoft
- Rick Hetherington, Sun
- Moin Qureshi, IBM
- Sean Lee, GA Tech
- Tim Sherwood, UCSB
- Pete Vogt, Intel
- Luiz Barroso, Google
- Scott Rixner, Rice

5:15 pm - Concluding Remarks


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Emery Berger
Assistant Professor
Dept. of Computer Science
University of Massachusetts, Amherst
www.cs.umass.edu/~emery