Re: toVHDL - lazy debug?

On Fri, 15 May 2015 18:07:49 -0400
"Jose M. Gomez Cama" <[email protected]> wrote:

> Dear Jan,
> 
> I think this should come from a non initialized
> Signal, or some forgot .next.
> 
> In any case, I have this lines just after the
> visit_Compare:
> 
>     def visit_Compare(self, node):
>         node.vhd = vhd_boolean()
>         self.generic_visit(node)
>         left, op, right = node.left,
> node.ops[0], node.comparators[0] if left.vhd is
> None: print(ast.dump(node))
> 
> The dump should provide you some hints.

Thanks, all fixed.  I had to put the dump at the
indicated line number, ~1006, and remove the
conditional, as I could not adapt it quickly. 

The problem was consistent use of bitwise
operators in a boolean expression. 

I noticed that if there is a mixture of logical
and boolean operators you get a nice error
message:

"myhdl.ConversionError: in
file /.../bcDscHndls.py, line 214: Not supported:
non-boolean argument in logical operator"

but no help for the completely stupid! 

Help much appreciated, now I'll check the rest of
this old code set. 

Kind regards, Jan Coombs. 
-- 

> > El 15/5/2015, a las 16:44, Jan Coombs
> > 
> > I have a convoluted module which passes
> > outline testing, and converts to ~500 lines
> > of Verilog, but will not convert to VHDL. 
> > 
> > On VHDL conversion failure the call stack has
> > entries for toVHDL and ast, and ends with the
> > message: 
> > 
> > "AttributeError: 'NoneType' object has no
> > attribute 'size'"
> > 
> > The resulting .vhd file has a complete list of
> > signals, but no code. 
> > 
> > Jan Coombs. 


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