Re: *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Hello World

Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:

> 
> Hello Josy,
> thank you.
> yes i saw that in VHDL there was this error.
> Therefore i tried it with verilog.
> But what i really do not understand what you mean you
> do not use read at all.
> Can you please explain this to me?
> When i have this:
> 
> I2C_SDAT = TristateSignal(False)
> 
> How would i have to write it to avoid this and
> how can i use this opendrain primitive than??
> 

Hello Günther,

The one essential part of my answer was that the conversion of 
TristateSignal() seems to be incorrect, both for Verilog and VHDL.
Also the VHDL conversion gives quite a few warnings:
** ToVHDLWarning: Output port is read internally: G_SENSOR_CS_N
** ToVHDLWarning: Port is not used: G_SENSOR_INT
** ToVHDLWarning: Output port is read internally: I2C_SCLK
** ToVHDLWarning: Output port is read internally: I2C_SDAT
** ToVHDLWarning: Signal is driven but not read: 
drive_spi_inst_read_Adr_inst_r_data2
** ToVHDLWarning: Signal is driven but not read: 
drive_spi_inst_read_Adr_inst_io
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_data1
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_2
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_1

Some of them are benign, some of them are to avoid.
Not that I am converting your code as you posted yesterday.
1. ** ToVHDLWarning: Output port is read internally: G_SENSOR_CS_N
This is (very probably) not your intention, and will (in VHDL) produce 
an *inout* port in stead of an *out* port. You can correct that by using 
local signals and assign the output port in a separate combinatorial 
procress.

2.** ToVHDLWarning: Port is not used: G_SENSOR_INT
You actually are not using it. 

3.** ToVHDLWarning: Output port is read internally: I2C_SCLK
This is like 1.

4.** ToVHDLWarning: Output port is read internally: I2C_SDAT
For a top-level module this can't be easily avoided. Note that in a VHDL 
top-file we would use a primitive like this:
	-- drive SDa via an open drain primitive
	od1 : opndrn port map(qs_SdaOut, IfSDa);
which would be warning-free

5.** ToVHDLWarning: Signal is driven but not read: 
drive_spi_inst_read_Adr_inst_r_data2

6.** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_data1
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_2
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_1
I'm not sure whether these three warnings should be there at all. You 
are using a Signal(intbv() as a constant. The generated VHDL is correct. 
The warning is correct though in stating that the Signal is not driven, 
read: depending on an input port.

Perhaps I shouldn't have mentioned my preference of splitting opendrain 
and tristate signals into inputs, outputs and for the tristate enable.
Now for your gw.py file this is no solution either as I understood that 
you are using the converted result as the top-file in your Quartus II 
project.


Regards,

Josy
------------------------------------------------------------------------------
One dashboard for servers and applications across Physical-Virtual-Cloud 
Widest out-of-the-box monitoring support with 50+ applications
Performance metrics, stats and reports that give you Actionable Insights
Deep dive visibility with transaction tracing using APM Insight.
http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
_______________________________________________
myhdl-list mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/myhdl-list