Re: Constant assignments in co-simulation

On 5/26/2015 7:10 AM, Nikolay Kavaldjiev wrote:
> Hi All,
>
> We have a co-simulation issue: when constants are assigned to signals in
> co-simulation, the assigned values are not visible in MyHDL.

In the example you linked there are two issues that
prevent it from working:  first, the initial values
is not (currently) used in the converted HDL.  The
`b` Signal in `concat_assign` will not be assigned
an initial value of `True`.

Second, you can't use and `always_comb` to assign
a Signal to a constant (as you comments indicate).

>
> The issue is demonstrated by the following gist:
> https://gist.github.com/nkavaldj/650fafbc3693f7a501e2
>
> The flow we use: MyHDL - > toVerilog -> Icarus
>
> Is there a known workaround?

I haven't run into this issue, a workaround would
be to use the constant directly and not create a
constant Signal.

Or use a dummy(ies) Signal in the `always_comb`
to preserve the const assignments.

     d1 = Signal(bool(0))
     d2 = Signal(bool(0))

     @always_comb
     def assign():
	# keep the combinatorial process
         d2.next = d1
	# assign constants
         x1.next = True
         x2.next = 0x55

     return assign

Or you could use the ROM design pattern:
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#rom-inference

Regards,
Chris


------------------------------------------------------------------------------
One dashboard for servers and applications across Physical-Virtual-Cloud 
Widest out-of-the-box monitoring support with 50+ applications
Performance metrics, stats and reports that give you Actionable Insights
Deep dive visibility with transaction tracing using APM Insight.
http://ad.doubleclick.net/ddm/clk/290420510;117567292;y