VHDL converted ConcatSignal

I started writing this when I noticed that the new (allowing constants) 
ConcatSignal doesn't produce VHDL that coerces a signed intbv signal to 
unsigned such that (at least in Vivado) an error occurs. In producing a 
minimal non-working example, I've noticed some other peculiarities in 
conversion.

I say the new ConcatSignal, but it might still be present in the older code.

The following gist gives an example of code causing a problem, along 
with generated output and my comments:

https://gist.github.com/hgomersall/cf8a47e7f6929564addd

The work around for the above is fairly simple and neat (and arguably 
better as it makes the signedness explicit) by having an interim 
unsigned signal. This is shown in the second comment of the above gist.

FYI: I get a similar complaint if concat_sig_in is set to be a single bit:

concat_sig_in = ConcatSignal(sig_in(1), intbv(0)[9:])

in which case I get an error along the lines of "indexed name is not a 
std_ulogic".

Cheers,

Henry

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