Re: VHDL converted ConcatSignal

On 27/05/15 13:57, Josy Boelen wrote:
> 3. I don't have the issue when taking a subscript instead of a slice,
> and neither should you because a single bit from either a signed or an
> unsigned still is a std_logic.

Yes, I think I was wrong on this - the problem was a zero length vector, 
which Python is quite happy with but Vivado baulks at (I assume because 
it's invalid VHDL or something).

Cheers,

Henry

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