Re: VHDL converted ConcatSignal

On 27/05/15 14:20, Josy Boelen wrote:
>>> > >3. I don't have the issue when taking a subscript instead of a slice,
>>> > >and neither should you because a single bit from either a signed or an
>>> > >unsigned still is a std_logic.
>> >
>> >Yes, I think I was wrong on this - the problem was a zero length vector,
>> >which Python is quite happy with but Vivado baulks at (I assume because
>> >it's invalid VHDL or something).
> A zero-length vector is invalid VHDL, and perhaps we should have MyHDL
> complain about that too? But how do you fabricate a zero-length vector in
> MyHDL?

Hmmm good question. I suspect this is a non-issue that some other 
problem caused to be shown. I've removed such a case from my test suite 
and caught it earlier, so I'm not concerned with it anymore. I suspect 
if it is a real problem it will be corrected by proper coercion of types.

Cheers,

Henry


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