Re: Array of constants and code generation

> I'm trying to implement a cordic module to calculate the phase of a
> vector with rectangular coordinates x and y.  The cordic is a full
> parallel pipelined architecture; the vector rotations are generated in 
a 
> loop.  The angles are precalculated as integers in a list.
> The code simulates perfectly; but code generation with toVHDL
> or toVerilog fails with this error:
> 
> ConversionError: in file 
> 
C:\Users\thomas\devel\mytss5\dist\components\_Pythonlib\pmc4\hardware\ip
\cordic.py, 
> line 40:
>      Object type is not supported in this context: angles, <type 
'list'>
> 
> I tried a tuple instead of a list but conversion failed as well.
> 
> How can I rewrite the code for conversion?

This converts:
SCALE = 2000
N = 10

def Cordic(clk,  x, y, phase):

    xi = [Signal(intbv(0, min = - 2**12, max = 2**12)) for _ in 
range(N)]
    yi = [Signal(intbv(0, min = - 2**12, max = 2**12)) for _ in 
range(N)]
    zi = [Signal(intbv(0, min = - 2**11, max = 2**11)) for _ in 
range(N)]

    angles = tuple([int(round(math.atan(2**-i) * SCALE / 2 / math.pi)) 
for i in range(N)])

    @always_seq(clk.posedge, reset = None)
    def doit():
        if x < 0:
            xi[0].next = -x
            yi[0].next = -y
            zi[0].next = SCALE // 4 * 3
        else:
            xi[0].next = x
            yi[0].next = y
            zi[0].next = SCALE // 4

        for i in range(9):
            aa = angles[i]
            if yi[i] < 0:
                xi[i+1].next = xi[i] - (yi[i] >> i)
                yi[i+1].next = yi[i] + (xi[i] >> i)
                zi[i+1].next = zi[i] + aa
            else:
                xi[i+1].next = xi[i] + (yi[i] >> i)
                yi[i+1].next = yi[i] - (xi[i] >> i)
                zi[i+1].next = zi[i] - aa

#         print(xi[N-1], yi[N-1], zi[N-1])
        phase.next = zi[N-1]

    return  doit

By introducing the variable *aa* and coercing *angles* into a tuple we 
get plausible VHDL code.
I agree that  *indexing an array of constants* would looks nice, and 
probably is what you expected. But I'm almost 100% sure the 
synthesizer/mapper will generate the same element usage for both.
I had to disable the print statement as that doesn't convert when using 
parenthesis and without it will emit writelines, which is probably not 
intended either.

Regards,

Josy




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