Re: Constant assignments in co-simulation

Hi All,

To close this thread, I give a summary and a workaround, which can also be
found in the original gist:
https://gist.github.com/nkavaldj/650fafbc3693f7a501e2

==============

The Problem

When we do MyHDL co-simulation using Icarus Verilog simulator, we have the
following problem: if in the converted MyHDL code we have a combinatorial
assignment of type

OutPort.next = CONSTANT

, where OutPort is an output port of the co-simulated module and CONSTANT
is some constant value, then during the co-simulation, in MyHDL we do not
see on OutPort value CONSTANT.

The problem is demonstrated by the code in cosim_issue.py given in the gist
above. There we have the MyHDL module "const_assign":

def const_assign(x, y, aBit, aByte):
    @always_comb
    def logic():
        y.next = x + 5
        aBit.next = True
        aByte.next = 55
    return logic

, which we convert to Verilog:

module const_assign (
    x,
    y,
    aBit,
    aByte
);
input [7:0] x;output [7:0] y;wire [7:0] y;output aBit;wire aBit;output
[7:0] aByte;wire [7:0] aByte;
assign y = (x + 5);assign aBit = 1'b1;assign aByte = 55;
endmodule

, and then we co-simulate with Icarus Veriog.

During co-simulation we expect to see the output ports aBit and aByte of
the co-simulated module to be assigned values True and 55 respectively.
However, the values that we actually see are different, False and 0. These
are the default values of the signals my_bit and my_byte connected to the
co-simulated module.

The Reason

We are not sure what the reason for this problem is, but what causes the
problem seams to be a Verilog continuous assignments of type:

assign OutPort = CONSTANT

The reason might be a VPI issue?!

A Workaround

We managed to to avoid the problem by slightly modifying the MyHDL module
to:

def const_assign(x, y, aBit, aByte):
    @always_comb
    def logic():
        dummy = 0
        y.next = x + 5
        aBit.next = True
        aByte.next = 55
    return logic

The only difference with the previous version of the module is the addition
of the dummy assignment dummy = 0, which serves no other purpose, but to
alter the generated Verilog:

module const_assign (
    x,
    y,
    aBit,
    aByte
);
input [7:0] x;output [7:0] y;reg [7:0] y;output aBit;reg aBit;output
[7:0] aByte;reg [7:0] aByte;
always @(x) begin: CONST_ASSIGN_LOGIC
    reg dummy;
    dummy = 0;
    y = (x + 5);
    aBit = 1'b1;
    aByte = 55;end
endmodule

By adding the dummy assignment to our @always_comb section we avoid the
Verilog continuous assignments that cause our problem, and instead of them
we get a combinatorial Verilog process, which co-simulates fine.



Regards,

Nikolay

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