Re: Mixing MyHDL-generated source with other code

On 06/05/15 18:54, Ben Reynwar wrote:
> At the moment pyvivado is doing four fairly independent things for me:
>
> 1) I use it as a build system to keep track of which modules depend on 
> which other modules and IP blocks and to specify how files that need 
> to be generated are generated.
> 2) I use it to run python unittests (very similar to what you do with 
> veriutils)
> 3) I use it to automate Vivado (simulation, synthesis, implementation 
> and deployment)
> 4) I use it to communicate with the FPGA from python.

Hi Ben (and all),

I've been thinking a bit more about this (in the context of every call 
to vivado taking an age to run) and I've just taken a bit of a look at 
your code. I'm sure Veriutils could benefit from the build system you 
offer. You've clearly put a lot of work into the interaction with Vivado 
and it would be stupid for me to replicate it all (Veriutil's 
interaction is very much simpler - a basic tcl script that is fleshed 
out with a template and then executed).

There's the mucky area around wrapping V* code, which you attack with 
your python function to generate an interface. My experience so far has 
been there are a few things that one wants to consider in wrapping 
existing code:
1) There are the port mappings (which may include different names).
2) Type conversions.
3) Ports held as a constant.
4) other things I've not thought of...

I dare say it would be possible to have a way of formalising those 
aspects, which could then be used to auto-generate wrappers around V* 
code. For some piece of VHDL (say), I currently have a VHDL wrapper as 
well as a vhdl_code snippet in the respective myhdl function.

I think this could be a really useful bit of code to break out as a 
separate project. I think it would make interaction between myhdl and 
vhdl much easier.

Cheers,

Henry

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