Re: Mixing MyHDL-generated source with other code

On 14/06/15 06:32, Ben Reynwar wrote:
> You should be able to take advantage of pyvivado Vivado stuff just by 
> using the `pyvivado.project` module.  You could just use that along 
> with all the V* files that you generated using Veriutils.  The main 
> speedup you get is that the project only gets regenerated if the files 
> have changed, which doesn't make much difference during development 
> but is a big plus when you're running unit tests later.  Still 
> annoyingly slow though!
>

Yeah, it is crap. There is a huge overhead in doing anything in Vivado - 
all my tests are creating new instances which takes ~7 seconds or so

> If I understand your comments on wrapper generation, you're suggesting 
> something similar to what I'm doing with the interface functions but 
> more formalized.  I could then use that same definition to generate 
> VHDL wrappers or a MyHDL wrapper. Is that correct?

Yeah exactly. Some sort of simple interface language/definition from 
which interface wrappers can be generated. Certainly, it's a common 
problem in myhdl that is in need of a neat solution.

That said, what does the new use_std_logic flag do? Is that per-module?

Cheers,

Henry

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