to_VHDL() conversion error: 'intbv' object has no attribute '__name__'

I'm working on some toy problems from projecteuler.org to get a better handle on myHDL and have run into a problem converting to VHDL.

As far as I can tell, it's something to do with mysum, fib_r1, or fib_r2, but I can't figure out what aspect is a problem.  Before the wall of text that is the code and the error code, I have 2 questions: 1) what's the specific problem I'm running into here? 2) If I wasn't emailing this list, where is the right place for me to look for solutions to this problem?

Here's my code:

from myhdl import *

import unittest
from unittest import TestCase


def euler2(results, results_valid, n, clk, reset):
    """ implement a solution in hardware to https://projecteuler.net/problem=2 """

    even = Signal(bool())
    #mysum, fib_r1, fib_r2 = [Signal(intbv(1, 1, n*10)) for i in range(3)]
    mysum = Signal(intbv(1,1,40000000))
    fib_r1 = Signal(intbv(1,1,40000000))
    fib_r2 = Signal(intbv(1,1,40000000))
    results_int = Signal(intbv(0, 0, 5000000))

    @always_comb
    def a():
        even.next = True if mysum(0) == 0 else False
        results_valid.next = True if mysum >= n else False
     #   results_valid.next = results_int(0)
        results.next = results_int

    @always_comb
    def c():
        mysum.next = fib_r1 + fib_r2

    @always_seq(clk.posedge, reset)
    def b():
        fib_r1.next = mysum
        fib_r2.next = fib_r1
        if even:
            results_int.next = results_int + mysum
        #results_int.next = results_int + 1
    return a, b, c
    #return a, b

And here's the unit test:

class TestEuler2(TestCase):
    def setUp(self):
        self.reset = ResetSignal(0, active=1, async=True)
        self.results_valid, self.clk = [Signal(bool()) for i in range(2)]
        self.results = Signal(intbv(0, 0, 5000000))
        self.clk_inst = self.run_clk(self.clk)

    def run_clk(self, clk):
        half_period = delay(10)

        @always(half_period)
        def clkgen():
            clk.next = not clk

        return clkgen

    def euler2_py(self, n):
        f1 = 1
        f2 = 1
        mysum = 0
        print " "
        while (f1 + f2) < n:
            mysum = mysum + f1 + f2
            f1, f2 = f1 + (2 * f2), (2 * f1) + (3 * f2)
        return mysum

    def checkResult(self, i, results, results_valid, clk, reset):
        reset.next = 1
        yield clk.negedge
        reset.next = 0
        while 1:
            yield clk.negedge
            if results_valid:
                self.assertEqual(results, self.euler2_py(i),
                                 "does " + str(results) + " == " + str(self.euler2_py(i)) + " for i == " + str(i))
                raise StopSimulation

    def test100(self):
        i = 100
        dut = traceSignals(euler2, self.results, self.results_valid, i, self.clk, self.reset)
        check = self.checkResult(i, self.results, self.results_valid, self.clk, self.reset)
        Simulation(dut, check, self.clk_inst).run(300000)
        euler_inst = toVHDL(euler2, self.results, self.results_valid, i, self.clk, self.reset)

    def test10000(self):
        i = 10000
        dut = euler2(self.results, self.results_valid, i, self.clk, self.reset)
        check = self.checkResult(i, self.results, self.results_valid, self.clk, self.reset)
        Simulation(dut, check, self.clk_inst).run(300000)

    def test4000000(self):
        i = 4000000
        dut = euler2(self.results, self.results_valid, i, self.clk, self.reset)
        check = self.checkResult(i, self.results, self.results_valid, self.clk, self.reset)
        Simulation(dut, check, self.clk_inst).run(300000)
        #euler_inst = toVHDL(euler2, self.results, self.results_valid, 4000000, self.clk, self.reset)



unittest.main()

And here's the run:

$ python euler2.py


E

.

.
======================================================================
ERROR: test100 (__main__.TestEuler2)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "euler2.py", line 81, in test100
    euler_inst = toVHDL(euler2, self.results, self.results_valid, 100, self.clk, self.reset)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 203, in __call__
    _convertGens(genlist, siglist, memlist, vfile)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 461, in _convertGens
    v.visit(tree)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1224, in visit_Module
    self.visit(stmt)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1631, in visit_FunctionDef
    self.visit_stmt(node.body)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1432, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 872, in visit_Assign
    self.visit(rhs)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1073, in visit_IfExp
    self.visit(node.test)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1012, in visit_Compare
    self.visit(node.left)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 981, in visit_Call
    self.write(f.__name__)
  File "/usr/lib/python2.7/site-packages/myhdl/_Signal.py", line 494, in __getattr__
    return getattr(self._val, attr)
AttributeError: 'intbv' object has no attribute '__name__'

----------------------------------------------------------------------
Ran 3 tests in 0.282s

FAILED (errors=1)
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