Re: YOSYS

On 8/31/2015 2:43 PM, Edward Vidal wrote:
> Hello All,
 >
 > From the yosys manual:
 > "The proposed custom HDL synthesis tool should be
> licensed under a Free and Open Source Software (FOSS) licence. So an
> existing FOSS Verilog or VHDL synthesis tool would have been needed
> as basis to build upon. The main advantages of choosing Verilog or
> VHDL is the ability to synthesize existing HDL code and to mitigate
> the requirement for circuit-designers to learn a new language. In
> order to take full advantage of any existing FOSS Verilog or VHDL
> tool, such a tool would have to provide a feature-complete
> implementation of the synthesizable HDL subset."
 > 
https://github.com/develone/raspberrypi2_yocto/blob/master/doc/yosys_manual.pdf
 >
> Regards Edward Vidal


What in the world is this supposed to be in
context to?  Is this intended to be part of
the previous thread?  Or a post prematurely
sent?  What does it have to do with MyHDL?

Regards,
Chris



------------------------------------------------------------------------------