Conversion generates invalid VHDL

Hi,

I've noticed that the following MyHDL code:

###
from myhdl import *

def test(clk_i, data_i, data_o):
    @always(clk_i.posedge)
    def logic():
        start_idx_v = intbv(0, min=0, max=1 + 15)
        for i in range(start_idx_v, 1 + 15):
            data_o.next[i] = data_i[i]
    return instances()

if __name__ == "__main__":
    clk_i = Signal(bool(0))
    data_i = Signal(intbv(0)[16:])
    data_o = Signal(intbv(0)[16:])
    toVHDL(test, clk_i, data_i, data_o)
###

generates invalid VHDL code:

###
TEST_LOGIC: process (clk_i) is
    variable start_idx_v: unsigned(3 downto 0);
begin
    if rising_edge(clk_i) then
        start_idx_v := to_unsigned(0, 4);
        for i in start_idx_v to (1 + 15)-1 loop
            data_o(i) <= data_i(i);
        end loop;
    end if;
end process TEST_LOGIC;
###

The problem is that VHDL doesn't allow unsigned objects in for loop bounds.
At the very least, there should be a type conversion to an integer:

        for i in to_integer(start_idx_v) to (1 + 15)-1 loop

Regards,
Guy.


Guy Eschemann
FPGA Consultant
noasic GmbH
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
[email protected] <[email protected]>
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