Re: Conversion generates invalid VHDL

Hi Josy,

I don't see anything in the VHDL standard stating that the loop range must
be constant. That would be quite a limitation. The only requirement is that
of a discrete range.

Regards,
Guy.

On Thu, Oct 1, 2015 at 2:42 PM, Josy Boelen <[email protected]> wrote:

>
> > def test(clk_i, data_i, data_o):
> >      <at> always(clk_i.posedge)
> >     def logic():
> >         start_idx_v = intbv(0, min=0, max=1 + 15)
> >         for i in range(start_idx_v, 1 + 15):
> >             data_o.next[i] = data_i[i]
> >     return instances()
> >
> > if __name__ == "__main__":
> >     clk_i = Signal(bool(0))
> >     data_i = Signal(intbv(0)[16:])
> >     data_o = Signal(intbv(0)[16:])
> >     toVHDL(test, clk_i, data_i, data_o)
>
> Hi Guy,
>
> Any particular reason you want to write it like that?
> I'd say using an intbv as an argument in the for-loop range is
> inappropriate and the conversion should detect that and raise an error. It
> may simulate fine, though.
> Anyway VHDL requires the for-loop range to be constant and I'm not sure
> the integer() cast will work either.
>
> Regards,
>
> Josy
>
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