Re: Conversion generates invalid VHDL

> I don't see anything in the VHDL standard stating that the loop range 
must be constant. That would be quite a limitation. The only requirement 
is that of a discrete range.
Guy,

Correct. Using _variables_ in the range specification will simulate but 
not synthesise (because the compiler will not know how to unroll the 
loop). As a consequence using this construct in an @always(clk.posedge) 
will not make sense, so flagging it with an error/warning would be most 
appropriate. Note that Verilog too expects static arguments.

Regards,

Josy


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