Re: test SDRAM_Controller

Edward Vidal <[email protected]> Thu, 15 Oct 2015 15:38:34 +0000 (UTC)
Newsgroups gmane.comp.python.myhdl
Message-ID <[email protected]>
Chris
Xstools, opencv all work okay on yocto Pi2B.

Yocto Pi2B fails

root@raspberrypi2:~/SDRAM_Controller# python
Python 2.7.9 (default, Sep 12 2015, 14:03:04) 
[GCC 4.9.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.

RaspBian Pi2B okay 
vidal@raspberrypi /usr/lib/python2.7 $ python 
Python 2.7.9 (default, Mar  8 2015, 00:52:26) 
[GCC 4.9.2] on linux2
Type "help", "copyright", "credits" or "license" for more information.

Ubuntu x86_64 okay
Python 2.7.3 (default, Sep 26 2013, 20:03:06) 
[GCC 4.6.3] on linux2
Type "help", "copyright", "credits" or "license" for more information
I tried 2to3 -l -w -v sdram.py2to3 -l -w -v test_controller.py2to3 -l -w -v test_sdram.pypython3 test_sdram.py
root@raspberrypi2:~/SDRAM_Controller# python3 test_controller.py
Traceback (most recent call last):
  File "test_controller.py", line 2, in <module>
    from SdramCntl import *
  File "/home/root/SDRAM_Controller/SdramCntl.py", line 3, in <module>
    from sd_intf import *
  File "/home/root/SDRAM_Controller/sd_intf.py", line 83
    addr = 0
           ^
TabError: inconsistent use of tabs and spaces in indentationfix the above error which has several lines with an extra space.Finally get back to same error 
python3 test_controller.py
Traceback (most recent call last):
  File "test_controller.py", line 30, in <module>
    sdram_Inst = sdram(clk_i,sd_intf_Inst,show_command=False)
  File "/home/root/SDRAM_Controller_old/sdram.py", line 51, in sdram
    @always(clk.posedge)
  File "/usr/local/lib/python3.4/site-packages/myhdl-1.0.dev0-py3.4.egg/myhdl/_always.py", line 59, in _always_decorator
    return _Always(func, args)
  File "/usr/local/lib/python3.4/site-packages/myhdl-1.0.dev0-py3.4.egg/myhdl/_always.py", line 78, in __init__
    symdict.update(zip(freevars, closure))
  File "/usr/local/lib/python3.4/site-packages/myhdl-1.0.dev0-py3.4.egg/myhdl/_always.py", line 77, in <genexpr>
    closure = (c.cell_contents for c in func.__closure__)
ValueError: Cell is empty
 Regards
Edward Vidal Jr. e-mail [email protected] 915-595-1613 


     On Wednesday, October 14, 2015 6:43 PM, Christopher Felton <[email protected]> wrote:
   

 Edward,

Do you have the full Python version for both systems?
The RPi is 2.7.? and the other system is?

Regards,
Chris

On 10/14/15 6:54 PM, Edward Vidal wrote:
>  Hello All,
>
> Testing https://github.com/udara28/SDRAM_Controller.git
>
> python Conversion generates on Raspberry Pi 2B
> -rw-r--r--  1 root root 10774 Oct 14 19:48 MySdramCntl.v
> -rw-r--r--  1 root root 12320 Oct 14 19:48 MySdramCntl.vhd
> -rw-r--r--  1 root root  4346 Oct 14 19:48 pck_myhdl_10.vhd
>
> This works okay on several systems see below.
>
> python test_controller.py on Raspberry Pi 2B
> Traceback (most recent call last):
>    File "test_controller.py", line 30, in <module>
>      sdram_Inst = sdram(clk_i,sd_intf_Inst,show_command=False)
>    File "/home/root/SDRAM_Controller/sdram.py", line 51, in sdram
>      @always(clk.posedge)
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 59, in _always_decorator
>      return _Always(func, args)
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 78, in __init__
>      symdict.update(zip(freevars, closure))
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 77, in <genexpr>
>      closure = (c.cell_contents for c in func.__closure__)
> ValueError: Cell is empty
>
> python test_controller.py
> vidal@vidal-MX6438:~/wkg/SDRAM_Controller$ python test_controller.py
>  BANK 0 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>  BANK 1 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>  BANK 2 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>  BANK 3 STATE : [CHANGE] Uninitialized -> Initialized @  3999
> --------------------------
>  Mode  | CAS  |  Burst
> --------|-------|---------
>  Burst  | 3    |  1
> --------------------------
>  DATA : [WRITE] Addr: 120  Data: 23
>  SDRAM : [READ] Commnad registered
>  STATE : [READ] Data Ready @  4167  value :  23
> Data Value :  23  clk :  4169
> <class 'myhdl._SuspendSimulation'>: Simulated 7500 timesteps
>
> Regards,
>
> Edward Vidal Jr. e-mail [email protected] 915-595-1613
>
>
> ------------------------------------------------------------------------------
>
>
>
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