adding files to top-level with rhea

Hello All,

Yosys & arachne-pnr appear to work very well compared to Xilinx ISE. 
It takes 2:41 to generate xula2.bit, while it only takes 0:35 to 
generate the catboard.bin.

On the RPi2B with CAT-Board the first 2 leds appeared to always be on.
See the changes to blink.py in the file attached chgs_blink.txt. 
I choose 12000000 since the freq. on my XulA2-LX9 is 12000000 Hz.
Using 1440000 on the XulA2-LX9 would be 8.333333 times.
Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
the same rate as leds on CAT-Board with RPi2B.
  
I generated the docs in both html & latexpdf formats.

Running make in rhea/test appears to work okay.
The test_models/test_fx2_model.py just hangs up. Should the be expected
at this point?

In the file ex_xula2.py I added the flow.add_files line.
    flow.add_files('jpeg_cat.v')
    flow.run()
Running ISE I see the file jpeg_cat.v is now part of the project.
What do I need to do, to have jpeg_cat.v instantiated in the xula2.v?
Or do I have to do this manually?
    // Inputs
    reg [9:0] left_i;
    reg [9:0] sam_i;
    reg [9:0] right_i;
    reg [3:0] flgs_i;
    reg update_i;
    reg clock;

    // Outputs
    wire [9:0] res_o;
    wire update_o;

    // Instantiate the Unit Under Test (UUT)
    jpeg_cat uut (
        .left_i(left_i), 
        .sam_i(sam_i), 
        .right_i(right_i), 
        .flgs_i(flgs_i), 
        .update_i(update_i), 
        .res_o(res_o), 
        .update_o(update_o), 
        .clock(clock)
    );

Does anyone have a MyHDL or Verilog for a DCM?I have been using the one in Xess VHDL_Lib

Regards,

 Edward Vidal Jr. e-mail [email protected] 915-595-1613

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Modifications to blink.py on RPi2B used to create catboard.bin.
--- blink.py	2015-12-14 11:03:16.519999868 +0000
+++ blink.py.tmp	2015-12-14 11:02:09.009999894 +0000
@@ -9,12 +9,12 @@
 
     nled = len(led)
     maxcnt = int(clock.frequency)
-    cnt = Signal(intbv(0,min=0,max=maxcnt))
+    cnt = Signal(intbv(0,min=0,max=12000000))
     toggle = Signal(bool(0))
 
     @always_seq(clock.posedge, reset=reset)
     def rtl():
-        if cnt == maxcnt-1:
+        if cnt == 12000000:
             cnt.next = 0
             toggle.next = not toggle
         else:
Modifications to blink.py on Ubuntu used to create xula2.bit.

--- blink.py	2015-12-21 05:47:24.931919453 -0700
+++ blink.py.tmp	2015-12-21 05:47:09.387919627 -0700
@@ -9,12 +9,12 @@
 
     nled = len(led)
     maxcnt = int(clock.frequency)
-    cnt = Signal(intbv(0,min=0,max=maxcnt))
+    cnt = Signal(intbv(0,min=0,max=1440000))
     toggle = Signal(bool(0))
 
     @always_seq(clock.posedge, reset=reset)
     def rtl():
-        if cnt == maxcnt-1:
+        if cnt == 1440000:
             cnt.next = 0
             toggle.next = not toggle
         else:


Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
the same rate as leds on CAT-Board with RPi2B.