Asynchronous double port RAM

Hi,

I am experimenting with asynchronous DPR (ie : with 2 clock domains)

Here is my code :

def MemoryGene1000Hz(
                      # Port A
                      clka,
                      addra,
                      wea,
                      dia,
                      ena,
                      doa,

                      # Port B
                      clkb,
                      addrb,
                      web,
                      dib,
                      enb,
                      dob
                     ):

     data_length = len(dia)

     # Instanciate RAM array
     ram = [Signal(intbv(0)[data_length:]) for i in range(2**len(addra))]

     # Init RAM with full scale sinus (48 samples)
     scale_factor = (2**(data_length-1)) - 1
     for i in range(48) :
         v = int(sin(i*2*pi/48) * scale_factor)
         ram[i] = Signal(intbv(v)[data_length:])
         #print(i, "%6.6X" % ram[i])

     @always(clka.posedge)
     def portA():
         if ena :
             doa.next = ram[addra]
             if wea :
                 ram[addra].next = dia

     @always(clkb.posedge)
     def portB():
         if enb :
             dob.next = ram[addrb]
             if web :
                 ram[addrb].next = dib

     return portA, portB


def convert():
     from myhdl import toVHDL

     clka  = Signal(bool(0))
     addra = Signal(intbv(0)[8:])
     wea   = Signal(bool(0))
     dia   = Signal(intbv(0)[24:])
     ena   = Signal(bool(0))
     doa   = Signal(intbv(0)[24:])

     clkb  = Signal(bool(0))
     addrb = Signal(intbv(0)[8:])
     web   = Signal(bool(0))
     dib   = Signal(intbv(0)[24:])
     enb   = Signal(bool(0))
     dob   = Signal(intbv(0)[24:])

     toVHDL.directory = "../vhdl"
     #toVHDL.std_logic_ports = True
     toVHDL(MemoryGene1000Hz,
            clka,
            addra,
            wea,
            dia,
            ena,
            doa,

            clkb,
            addrb,
            web,
            dib,
            enb,
            dob
           )

The generated VHDL code is not correct.
ram array is declared as a signal while this is not correct since 2 
processes access this object.
ram array should be declared as a shared variable. Right ?

Simulation seems to be ok.

Nicolas

-- 
*Nicolas PINAULT
R&D electronics engineer
*** [email protected] <mailto:[email protected]>

*AATON-Digital*
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Tel +33 4 7642 9550

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