Contribute to MyHDL through GSOC.

Hello Developers,
    I am Nagabhushan Baddi, a 3rd year electrical engineering student at
Indian Institute of Technology Roorkee. Being an enthusiastic digital
designer and a python programmer I find MyHDL a perfect project team to
work with during GSOC 2016.
I am familiar with programming in Verilog and Python for 2 years for now
and also with digital design and CMOS VLSI design.

    The project DDR3 controller is quite interesting and I would love to
contribute to this project. Since the project requires familiarity with
Verilog, Python and digital design, this should be a challenging and
interesting project experience for me.

    I am going through the MyHDL docs and the sample examples and quite got
acquainted with. I would love to hear from the mentors and other developers
and get help for me to get started.

Have a nice day.
Thank You.

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