Re: Asynchronous double port RAM

On 1/11/2016 7:45 AM, Nicolas Pinault wrote:

>>
>> I have no idea whether Vivado and ISE are also forgiving.
> The code I sent in my first message has been formatted following Xilinx
> rules.
> However, I did not tried to compile it with Xilinx tools. I'll have a
> try and tell you.
>>
>> Your other request: initialising the ram-array is not that much work.
>> I'll try to submit a PR shortly.
> That's good news :)


You can refer to the issue #105 for some info:
https://github.com/jandecaluwe/myhdl/issues/105

There has been some work that might be useful (or not):
https://github.com/jandecaluwe/myhdl/pull/102

Henry's first pass (see PR comments), we should limit
the feature to just "initial value" changes.
https://github.com/hgomersall/myhdl/tree/initial_value_support

I was assisting Henry some but I don't recall where I
(we) left off:
https://github.com/cfelton/myhdl/tree/initial_value_support

Regards,
Chris



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