Re: Asynchronous double port RAM

On 12/01/16 14:45, Christopher Felton wrote:
> On 1/11/2016 7:45 AM, Nicolas Pinault wrote:
> 
>>> >>
>>> >> I have no idea whether Vivado and ISE are also forgiving.
>> > The code I sent in my first message has been formatted following Xilinx
>> > rules.
>> > However, I did not tried to compile it with Xilinx tools. I'll have a
>> > try and tell you.
>>> >>
>>> >> Your other request: initialising the ram-array is not that much work.
>>> >> I'll try to submit a PR shortly.
>> > That's good news :)
> 
> You can refer to the issue #105 for some info:
> https://github.com/jandecaluwe/myhdl/issues/105
> 
> There has been some work that might be useful (or not):
> https://github.com/jandecaluwe/myhdl/pull/102
> 
> Henry's first pass (see PR comments), we should limit
> the feature to just "initial value" changes.
> https://github.com/hgomersall/myhdl/tree/initial_value_support
> 
> I was assisting Henry some but I don't recall where I
> (we) left off:
> https://github.com/cfelton/myhdl/tree/initial_value_support

It's working*, it just needs the tests to be written. I implemented and
tested it against Vivado, which depended on an external library a wrote,
which wasn't acceptable to Jan for inclusion.

I've basically had other things that have been absorbing (literally) all
my time for quite a while. I'm likely to get back to some FPGA work
soonish though.

I think that PR suggests the suitable test scenario if you fancy a bash.

Cheers,

Henry

*it _was_ working - I haven't checked it against a recent master.

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