Re: parallel to serial

On 15/01/16 18:45, Edward Vidal wrote:
> Hello All,
> I can not believe that 3 lines are such a problem.
> This t.next = (temp[36:35]) generates   t <= temp(36-1 downto 35)(0);
> which does not appear correct.

Why not?

But still, if working with single bits, why don't you simply
assign an index instead of a slice?

> This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0);
> which be taking the lower  34 bits to upper 34 of temp.

That makes no sense in MyHDL, and will not simulate. Hence, you
cannot draw any conclusions from conversion, even if it doesn't complain.

Simulate first.

> I am using @always(clk.posedge) could this be the problem?

No.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com


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