Re: simulation appears okay when programmed not getting all signals.

Hi All,As I said in the previous e-mail.
For testing just para2ser on Xula2 & CAT-Board 

To get a bit (Xula2-LX9) or bin (CAT-Board) file I use "python ex_xula_sending.py" 
with Xilinx Tools on a  Ubuntu system.  

On a RPi2B with Yosys, Arachne-pnr, IcePack "python ex_sending.py" 
creates the files to program the ICE40. The gpio_test.py is used to read the GPIO on the RPi2B. 
Are you using you using ICECube2 to generate a bin file for ICE40?
I have been trying to get this installed on my Ubuntu system. 
The Diamond software installed 
I downloaded "diamond_3_6-base_x64-83-4-x86_64-linux.rpm" which I converted with  alien --scriptsdiamond_3_6-base_x64-83-4-x86_64-linux.rpm 
diamond-3-6-base-x64_3.6-84_amd64.debgenerated  with dpkg -i diamond-3-6-base-x64_3.6-84_amd64.debThe license.dat that has VENDOR_STRING="ispLEVER System with Synplicity \
        Pro 1" HOSTID=6c626def84d9
 was used for Diamond.
sudo cplattice/diamond/license.dat/usr/local/diamond/3.6_x64/bin/lin64/../../license/
When I execute "/usr/local/diamond/3.6_x64/bin/lin64/diamond"  my diamond gui appears.
I downloaded  iCEcube2_2015-08.tgz. After extraction I get iCEcube2setup_Oct_14_2015_1508.When I execute as root  ./iCEcube2setup_Oct_14_2015_1508
bash: ./iCEcube2setup_Oct_14_2015_1508: No such file or directory

What am I missing?
Does anyone have any ideas what I am doing wrong?
Regards,
 Edward Vidal Jr. e-mail [email protected] 915-595-1613 

    On Saturday, January 23, 2016 10:14 AM, Jan Coombs <[email protected]> wrote:
 

 On Sat, 23 Jan 2016 15:39:34 +0000 (UTC)
Edward Vidal <[email protected]> wrote:

> Hi All,
> Most of the files in the pc_fast_blinker_jpeg folder have 2
> options --test to run a simulation 
> 
> and --convert to create a Verilog file.  Trying to follow
> Chris's examples.

Ok, it is all new to me. Next time perhaps you could give clear
instructions. I missed the opportunity to interpret:

Hello All,   
    ran python test_sending31.py --test which generates tb.vcd 

into:

Hello All, ran 
  python test_sending31.py --test 
which generates tb.vcd 


I now have a tb.vcd file, so feel that with this mornings
work, and your additional hint I can now re-create your
work. 


> The file test_top.py imports several files
> 
> 
> from jpeg import dwt
> from signed2twoscomplement import signed2twoscomplement
> from l2r import lift2res
> from sh_reg import ShiftReg, toSig
> from para2ser import para2ser
> from div_clk import div_4
> from jpeg_sig import *
    
                      [Did I need to know that?]

> 
> Running "python test_top.py --test" is my overall goal. 

Ok dune it, seems to work, if this is what you expected:

jan:pc_fast_blinker_jpeg$ 
jan:pc_fast_blinker_jpeg$  python test_top.py --test
256 256
reset 1 
reset 0 
reset 1 
update firstBit 0000000000000000000000000000000 1 1 
first flgs firstBit 0000000000000000000000000000000 1 1 
2nd flg firstBit 0000000000000000000000000000001 1 1 
3rd flgs 0000000000000000000000000000011 1 
Right 010100100 164
31 bits 0000000000000000000000000000111 0 8 
31 bits 0000000000000000000000000001111 1 7 
31 bits 0000000000000000000000000011110 0 6 
31 bits 0000000000000000000000000111101 1 5 
31 bits 0000000000000000000000001111010 0 4 
31 bits 0000000000000000000000011110101 0 3 
31 bits 0000000000000000000000111101010 1 2 
31 bits 0000000000000000000001111010100 0 1 
LSB rht 0000000000000000000011110101001 0 0 
Sam 010100100 164
31 bits 0000000000000000000111101010010 0 8 
31 bits 0000000000000000001111010100100 1 7 
31 bits 0000000000000000011110101001000 0 6 
31 bits 0000000000000000111101010010001 1 5 
31 bits 0000000000000001111010100100010 0 4 
31 bits 0000000000000011110101001000101 0 3 
31 bits 0000000000000111101010010001010 1 2 
31 bits 0000000000001111010100100010100 0 1 
LSB sam 0000000000011110101001000101001 0 0 
Left 010011100 156
31 bits 0000000000111101010010001010010 0 8 
31 bits 0000000001111010100100010100100 1 7 
31 bits 0000000011110101001000101001000 0 6 
31 bits 0000000111101010010001010010001 0 5 
31 bits 0000001111010100100010100100010 1 4 
31 bits 0000011110101001000101001000100 1 3 
31 bits 0000111101010010001010010001001 1 2 
31 bits 0001111010100100010100100010011 0 1 
LSB lft 0011110101001000101001000100111 0 0 
fB0 0 
reset 1 
reset 0 
reset 1 
update firstBit 0000000000000000000000000000000 1 1 
first flgs firstBit 0000000000000000000000000000000 1 1 
2nd flg firstBit 0000000000000000000000000000001 1 1 
3rd flgs 0000000000000000000000000000011 1 
Right 010100100 164
31 bits 0000000000000000000000000000111 0 8 
31 bits 0000000000000000000000000001111 1 7 
31 bits 0000000000000000000000000011110 0 6 
31 bits 0000000000000000000000000111101 1 5 
31 bits 0000000000000000000000001111010 0 4 
31 bits 0000000000000000000000011110101 0 3 
31 bits 0000000000000000000000111101010 1 2 
31 bits 0000000000000000000001111010100 0 1 
LSB rht 0000000000000000000011110101001 0 0 
Sam 010100100 164
31 bits 0000000000000000000111101010010 0 8 
31 bits 0000000000000000001111010100100 1 7 
31 bits 0000000000000000011110101001000 0 6 
31 bits 0000000000000000111101010010001 1 5 
31 bits 0000000000000001111010100100010 0 4 
31 bits 0000000000000011110101001000101 0 3 
31 bits 0000000000000111101010010001010 1 2 
31 bits 0000000000001111010100100010100 0 1 
LSB sam 0000000000011110101001000101001 0 0 
Left 010100100 164
31 bits 0000000000111101010010001010010 0 8 
31 bits 0000000001111010100100010100100 1 7 
31 bits 0000000011110101001000101001000 0 6 
31 bits 0000000111101010010001010010001 1 5 
31 bits 0000001111010100100010100100010 0 4 
31 bits 0000011110101001000101001000101 0 3 
31 bits 0000111101010010001010010001010 1 2 
31 bits 0001111010100100010100100010100 0 1 
LSB lft 0011110101001000101001000101001 0 0 
fB1 0 
reset 1 
reset 0 
reset 1 
update firstBit 0000000000000000000000000000000 1 1 
first flgs firstBit 0000000000000000000000000000000 1 1 
2nd flg firstBit 0000000000000000000000000000001 0 0 
3rd flgs 0000000000000000000000000000011 1 
Right 010100100 164
31 bits 0000000000000000000000000000111 0 8 
31 bits 0000000000000000000000000001111 1 7 
31 bits 0000000000000000000000000011110 0 6 
31 bits 0000000000000000000000000111101 1 5 
31 bits 0000000000000000000000001111010 0 4 
31 bits 0000000000000000000000011110101 0 3 
31 bits 0000000000000000000000111101010 1 2 
31 bits 0000000000000000000001111010100 0 1 
LSB rht 0000000000000000000011110101001 0 0 
Sam 010011100 156
31 bits 0000000000000000000111101010010 0 8 
31 bits 0000000000000000001111010100100 1 7 
31 bits 0000000000000000011110101001000 0 6 
31 bits 0000000000000000111101010010001 0 5 
31 bits 0000000000000001111010100100010 1 4 
31 bits 0000000000000011110101001000100 1 3 
31 bits 0000000000000111101010010001001 1 2 
31 bits 0000000000001111010100100010011 0 1 
LSB sam 0000000000011110101001000100111 0 0 
Left 010100100 164
31 bits 0000000000111101010010001001110 0 8 
31 bits 0000000001111010100100010011100 1 7 
31 bits 0000000011110101001000100111000 0 6 
31 bits 0000000111101010010001001110001 1 5 
31 bits 0000001111010100100010011100010 0 4 
31 bits 0000011110101001000100111000101 0 3 
31 bits 0000111101010010001001110001010 1 2 
31 bits 0001111010100100010011100010100 0 1 
LSB lft 0011110101001000100111000101001 0 0 
fB2 0 
reset 1 
reset 0 
reset 1 
update firstBit 0000000000000000000000000000000 1 1 
first flgs firstBit 0000000000000000000000000000000 1 1 
2nd flg firstBit 0000000000000000000000000000001 0 0 
3rd flgs 0000000000000000000000000000011 1 
Right 010100100 164
31 bits 0000000000000000000000000000111 0 8 
31 bits 0000000000000000000000000001111 1 7 
31 bits 0000000000000000000000000011110 0 6 
31 bits 0000000000000000000000000111101 1 5 
31 bits 0000000000000000000000001111010 0 4 
31 bits 0000000000000000000000011110101 0 3 
31 bits 0000000000000000000000111101010 1 2 
31 bits 0000000000000000000001111010100 0 1 
LSB rht 0000000000000000000011110101001 0 0 
Sam 010011100 156
31 bits 0000000000000000000111101010010 0 8 
31 bits 0000000000000000001111010100100 1 7 
31 bits 0000000000000000011110101001000 0 6 
31 bits 0000000000000000111101010010001 0 5 
31 bits 0000000000000001111010100100010 1 4 
31 bits 0000000000000011110101001000100 1 3 
31 bits 0000000000000111101010010001001 1 2 
31 bits 0000000000001111010100100010011 0 1 
LSB sam 0000000000011110101001000100111 0 0 
Left 010100100 164
31 bits 0000000000111101010010001001110 0 8 
31 bits 0000000001111010100100010011100 1 7 
31 bits 0000000011110101001000100111000 0 6 
31 bits 0000000111101010010001001110001 1 5 
31 bits 0000001111010100100010011100010 0 4 
31 bits 0000011110101001000100111000101 0 3 
31 bits 0000111101010010001001110001010 1 2 
31 bits 0001111010100100010011100010100 0 1 
LSB lft 0011110101001000100111000101001 0 0 
fB3 0 
1 2 3
156 164 164
010011100 010100100 010100100
3 4 5
164 164 164
010100100 010100100 010100100
5 6 7
164 156 164
010100100 010011100 010100100
7 8 9
164 156 164
010100100 010011100 010100100
jan:pc_fast_blinker_jpeg$ 
jan:pc_fast_blinker_jpeg$ 

is this the expected output? 

Jan Coombs
--

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