(rhea) icestick_blinky_host.py
Edward Vidal <[email protected]> Fri, 5 Feb 2016 17:05:57 +0000 (UTC)
| Newsgroups | gmane.comp.python.myhdl |
|---|---|
| Message-ID | <[email protected]> |
Hi All,I am trying to add these memmap_command_bridge, glbl_timer_ticks, Barebone and FIFOBus cores from (rhea) icestick_blinky_host.py to my code. On the CAT-Board on pg 6 of the schematic the 100MHz oscillator provides signal USER_CLK which is connected to C8 of ICE40-HX8K-CT256. The catboard.pcf created with rhea, in the catboard.pcf file I see set_io clock C8. Do these 2 lines above have an impact on the ICE40 clock? clock=Clock(0, frequency=50e6) glbl = Global(clock, None) Running python input_clk.py --convert generates cat_top.v.Running python input_clk.py --build generates iceriver/catboard.v In the catboard.v I see wire cmd_inst_clock; which is not in cat_top.v. Also many of the modules in catboard.v have this linealways @(posedge cmd_inst_clock) begin What drives cmd_inst_clock? https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/input_examples/input_clk.py Thanks, Edward Vidal Jr. e-mail [email protected] 915-595-1613 ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140 _______________________________________________ myhdl-list mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/myhdl-list