how to make list of unequal-sized signals
David Belohrad <[email protected]> Thu, 25 Feb 2016 11:49:27 +0100
| Newsgroups | gmane.comp.python.myhdl |
|---|---|
| Message-ID | <[email protected]> |
Hi all, the problem is following: this is convertible, as all the signals in the array have the same length: multout = [Signal(intbv(0, min=de.min*min(coeffs), max=de.max*max(coeffs))) for coeff in coeffs] this does not seem to be convertible, as the signals in the array have different lengths multout = [Signal(intbv(0, min=de.min*coeff, max=de.max*coeffs)) for coeff in coeffs] how to make the second construct behave as a simple list of different signals rather than an array? The first construct is converted into VHDL as an array: type t_array_multout is array(0 to 4-1) of unsigned(21 downto 0); signal multout: t_array_multout; evidently this cannot be with the second as in order to make the second one running it has to be exploded to individual items. any way how to achieve this? any hint very appreciated. thanks .d. ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=272487151&iu=/4140